edt_msdv.h

/*

* register definition for MSDV interface
* Xilinx bitfile.
*/

#ifndef _EDT_MSDV_H_
#define _EDT_MSDV_H_

#include "edt_ocx.h"

/*
* MSDV definitions.
*/
#define  MSDV_CLK_ENABLE        0x01010024
#define  MSDV_X_DATA            0x01010040
#define  MSDV_X_CONT            0x01010041
#define  MSDV_X_STAT            0x01010042
#define  MSDV_X_CONST           0x01010043
#define  MSDV_TEMPERATURE       0x01010044
#define  MSDV_RCV_CTRL          0x01010080
#define  MSDV_XMT_CTRL          0x01010081
#define  MSDV_DMA_TEST          0x01010082
#define  MSDV_SERIAL_DEV        0x01010088
#define  MSDV_CLK0_CFG_STAT     0x0101008c
#define  MSDV_CLK1_CFG_STAT     0x0101008d
/*
* SI 532x config/stat registers
*/
#define  SI532X_ENABLE          0x1
#define  SI432X_INC             0x2
#define  SI532X_DEC             0x4
#define  SI532X_LOL             0x10
#define  SI532X_C1B             0x20
#define  SI532X_C2B             0x40


#define  MSDV_CH0_PORT_CONFIG   0x01010090
#define  MSDV_CH0_DATA_CONFIG   0x01010091
#define  MSDV_CH0_REFRAME_COUNT 0x01010092
#define  MSDV_CH0_DISP_ERR_COUNT        0x01010093
#define  MSDV_CH0_CODE_ERR_COUNT        0x01010094
#define  MSDV_CH0_PORT_STATUS   0x01010095

#define  MSDV_CH1_PORT_CONFIG   0x01010098
#define  MSDV_CH1_DATA_CONFIG   0x01010099
#define  MSDV_CH1_REFRAME_COUNT 0x0101009A
#define  MSDV_CH1_DISP_ERR_COUNT        0x0101009B
#define  MSDV_CH1_CODE_ERR_COUNT        0x0101009C
#define  MSDV_CH1_PORT_STATUS   0x010100(D

#define  MSDV_CH2_PORT_CONFIG   0x010100B0
#define  MSDV_CH2_DATA_CONFIG   0x010100B1
#define  MSDV_CH2_REFRAME_COUNT 0x010100B2
#define  MSDV_CH2_DISP_ERR_COUNT        0x010100B3
#define  MSDV_CH2_CODE_ERR_COUNT        0x010100B4
#define  MSDV_CH2_PORT_STATUS   0x010100B5

#define  MSDV_CH3_PORT_CONFIG   0x010100B8
#define  MSDV_CH3_DATA_CONFIG   0x010100B9
#define  MSDV_CH3_REFRAME_COUNT 0x010100BA
#define  MSDV_CH3_DISP_ERR_COUNT        0x010100BB
#define  MSDV_CH3_CODE_ERR_COUNT        0x010100BC
#define  MSDV_CH3_PORT_STATUS   0x010100BD





/* MSDV_PORT_CONFIG */

#define  MSDV_OUT_ENABLE        0x1
#define  MSDV_XMIT_STDDEF       0x4
#define  MSDV_MUTE_INPUT        0x8
#define  MSDV_BYPASS            0x10
#define  MSDV_ERR_COUNT_EN      0x80

/* MSDV_DATA_CONFIG */

#define  MSDV_MODE_RAW          0
#define  MSDV_MODE_BIT_ALIGNED  1
#define  MSDV_MODE_DECODED      2
#define  MSDV_MODE_DATA         3
#define  MSDV_MODE_TS_FRAMES    4
#define  MSDV_MODE_TIMESTAMP    5
#define  MSDV_MODE_PRBS15       6
#define  MSDV_MODE_TEST         7

#define  MSDV_INVERT_PRBS       0x8
#define  MSDV_FILTER_IDLE       0x10

/* MSDV_PORT_STATUS */

#define MSDV_CARRIER_DETECT     1
#define MSDV_CHANNEL_RESET      2
#define MSDV_PLL_LOCK           4
#define MSDV_BIT_ALIGN          8
#define MSDV_TS_FRAME           0x10
#define MSDV_TS_206             0x20


#define  MSDV_BITFILE_VER       0x010100A0


/*
* registers 0 (PCD_CMD), 1 (PCD_DATA_PATH_STAT), 2 POCD_FUNCT), 3 (PCD_STAT),  0xf (PCD_CONFIG),
* 0x10 (SSD16_CHEN), 0x16 (SSD16_LSB), 0x18 (SSD16_UNDER) and 0x1b (SSD16_OVER) have
* the regular address definition with the standard bit placement and definition as follows:
* command - PCD_ENABLE bit 0x8 only, others are read/write but unused
* data_path - bits are read/write but not used
* funct - bits are read write but unused
* status - bit 0 indicates the sysclk DCM on the Xilinx is locked to the clock from the MSDV board
*/
#define MSDV_STAT_SYS_LOCKED            0x1

/*
* config - bit 0 is byteswap (PCD_BYTESWAP) and 3 is short swap (PCD_SHORTSWAP)
* channel enable - bit 0 and 1 enable channel 0 and 1
* lsb_first - bit 0 and 1 control channel 0 and 1
* underflow - bit 0 and 1 report status, bit 2 to 15 are always 0.
* overflow - bit 0 and 1 report status, bit 2 to 15 are always 0.
*/

/* channel enable bits in SSD16_CHEN  channel 0 to 3 enable channel 0 to 3 */
/* channel direction bits in SSD16_DIR  channel 0 to 3 control the direction */


/*
* program the Xilinx for channel 0 
* the data register is loaded with the bit file data. It is a fifo which holds 15 bytes
* the number of bytes in the fifo is read in the top 4 bist of the status register
* The CONT register controls the PROGL and INIT pins of each Xilinx, bit 4 controls which
* xilinx gets the data being loaded in the data register
* The STAT register reflects the status of the DONE and INIT pins.
* The constant register is written and read to determine if the ocm.bit file is loaded before
* attempting to load the individual channel xilinx.
*/

/* control register bits */
#define MSDV_CONT_CH0_INIT      0x1     /* one tristates INIT pin */
#define MSDV_CONT_CH0_PROG      0x2     /* one drives the PROG_L pin low (resets xilinx program) */
#define MSDV_CONT_ENABLE        0x20    /* enables the fifo, cclk and bit serializer */
#define MSDV_CONT_EN_FIFO       0x40    /* enables the fifo, cclk and bit serializer */

/* status bits */
#define MSDV_STAT_CH0_INIT      0x1     /* reads state of INIT pin */
#define MSDV_STAT_CH0_DONE      0x2     /* reads state of DONE pin */
#define MSDV_FCNT_MSK           0xf0
#define MSDV_FCNT_SHFT          4

#define MSDV_CONSTANT           0x10    /* fixed pattern in OCM_X_CONST register */


/*
* Enable Registers
*/
#define SYS_EN          0x04
/* read status in top bits */
#define SYS_LOCK        0x20

/*
* id string for ocm.bit
*/
#define MSDV_ID_STR     0x0101007d
/*
* id string for ocm mezzanine bit files
*/
#define MSDV_CH0_ID_STR 0x010100a0
/*
* both id registers can be written with the following commands
*/
#define MSDV_ID_SIZE            16

/*
*/


#endif

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