edt_ss_vco.h Source File

00001 
00002 #ifndef EDT_SS_VCO_H
00003 #define EDT_SS_VCO_H
00004 
00005 #ifdef DOXYGEN_SHOW_UNDOC
00006 
00010 #endif
00011 
00012 #define XTAL20          10000000.0
00013 #define XTAL40          20000000.0
00014 #define XTAL60          30000000.0
00015 
00016 #define XTAL_SS         10368100.0
00017 
00018 
00019 /* PCI SS */
00020 #define F_SS_LOW         120000000.0
00021 
00022 
00023 #define F_XILINX_307 200000000.0
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027 
00028 
00029 #define RDW m
00030 #define VDW n
00031 #define OD v
00032 
00033 
00034 EDTAPI
00035 double
00036 edt_find_vco_frequency_ics307(EdtDev *edt_p, double target,
00037                                 double xtal, edt_pll *pll, int verbose);
00038 
00039 EDTAPI
00040 double
00041 edt_find_vco_frequency_ics307_nodivide(EdtDev *edt_p, double target,
00042                                 double xtal, edt_pll *pll, int verbose);
00043 
00044 EDTAPI
00045 double
00046 edt_find_vco_frequency_ics307_raw(EdtDev *edt_p, double target,
00047                                 double xtal, edt_pll *pll, int verbose);
00048 
00049 EDTAPI
00050 double 
00051 edt_set_frequency_ics307(EdtDev *edt_p, 
00052                                                  double ref_xtal, 
00053                                                  double target,
00054                                                  int clock_channel,
00055                                                  int finaldivide);
00056 
00057 EDTAPI
00058 double 
00059 edt_set_frequency_fcipcd(EdtDev *edt_p, 
00060                                                  double target);
00061 
00062 EDTAPI
00063 void
00064 edt_set_out_clk_ics307(EdtDev * edt_p, edt_pll * clk_data, int clock_channel);
00065 
00066 
00067 
00068 #ifdef   __cplusplus
00069 }
00070 #endif
00071 
00072 #ifdef DOXYGEN_SHOW_UNDOC
00073  /* end weakgroup */
00074 #endif
00075 
00076 #endif
00077 
00078