edt_threep.h

#ifndef EDT_THREEP_REGS_H
#define EDT_THREEP_REGS_H

#include "edt_si5326.h"
#include "edt_si570.h"
#include "edt_s19250.h"

/* In these register names the _CH0_, _CH1_, and _CH2_ have been renamed 
   to _P0_, etc. to indicate that these are "ports" and not channels, because
   the DMA channels don't easily map to the ports on the 3P. The
   input channels are 0,1,2 for the three ports, but the output channels are 3,1,2 respectively.
   */


#define THREEP_DATA_PATH    0x0101004A


#define THREEP_P1_CONFIG0       0x010100A0
#define THREEP_P2_CONFIG0       0x010100C0

#define LOCK_REF        0x02
#define RX_SEL_MSK      0x0c
#define AUTO_DETECT     0x10
#define REMOTE_LOOP     0x20
#define LOCAL_LOOP      0x40
#define PRBS_EN 0x80


#define THREEP_P0_LIU_STATUS    0x01010081
#define RX_LOCKDET      0x1
#define TX_LOCKDET      0x2

#define THREEP_P1_CONFIG1       0x010100A1
#define THREEP_P2_CONFIG1       0x010100C1
#define CONFIG2511      0x03
#define PRE2511 0x0c
#define LOOPTIME        0x10

#define THREEP_P1_STATUS        0x010100A2
#define THREEP_P2_STATUS        0x010100C2
#define SPILL2511       0x01
#define PRBSPASS 0x02
#define RATE_DET_MSK 0x0c
#define LOS     0x10
#define LOL     0x20
#define SIG_DET 0x80

#define THREEP_P0_XCVR_STAT     0x01010083
#define THREEP_P1_XCVR_STAT     0x010100A3
#define THREEP_P2_XCVR_STAT     0x010100C3
#define SFPP_TXDIS      0x01
#define SFPP_PRES       0x20
#define SFPP_TXFAULT    0x40
#define SFPP_LOS        0x80
// added to bypass CDR on SFPP
#define SFPP_BYPASS 0x8

#define THREEP_P0_ENABLE        0x01010084
#define THREEP_P1_ENABLE        0x010100A4
#define THREEP_P2_ENABLE        0x010100C4
#define LIU_EN          0x01
#define TXPLL_EN        0x02
#define RXPLL_EN        0x10
#define SYS_LOCKED      0x20
#define THREEP_TX_LOCKED        0x40
#define THREEP_RX_LOCKED        0x80


#define THREEP_P0_RCV_FRAMING   0x01010085

#define THREEP_P1_RCV_FRAMING   0x010100A5
#define THREEP_P2_RCV_FRAMING   0x010100C5
/* Common: */
#define RESET_FRM       0x01
#define FRAME_EN        0x02
#define RX_DATA_SRC     0x0C
/* Port 0 specific: */
#define THREEP_10GBE_HI_BER 0x20
#define THREEP_10GBE_SH_LOCK    0x40
#define THREEP_10GBE_LINK_GOOD  0x80
/* Port 1,2 specific: */
#define DISABLE_SCRAM   0x10
#define SUSPEND_AQ      0x20
#define EN_PAR_CNT      0x40

#define THREEP_P0_RCV_FRM_COUNT_CTRL 0x0101008B
#define THREEP_ENABLE_FRM_COUNT 0x80
#define THREEP_FRM_COUNT_HOLD 0x01

#define THREEP_P0_10GBE_RCV_FILTER      0x01010086
#define THREEP_10GBE_DIS_IDLE_FILT 0x08
#define THREEP_P0_RCV_FILTER    0x01010086
#define THREEP_P1_RCV_FILTER    0x010100A6
#define THREEP_P2_RCV_FILTER    0x010100C6
/* SDH: */
#define OVERHEAD_ONLY 0x01
/* 1GBE: */
#define FORCE_ALL_DATA 0x08

#define THREEP_P1_RCV_STATUS    0x010100A7
#define THREEP_P2_RCV_STATUS    0x010100C7
#define FRAMED 0x01

#define THREEP_P1_RCV_FRAME_STATUS      0x010100A8
#define THREEP_P2_RCV_FRAME_STATUS      0x010100C8
#define BIT_SYNC        0x01
#define BYTE_SYNC       0x02
#define MATCH_CNT       0x0C
#define DROP_CNT        0x30
#define FOUND   0x40
#define LOCKED  0x80

#define THREEP_P0_OUTPUT_DATA_SEL       0x01010089
#define THREEP_10GBE_TXDBG 0x06
#define THREEP_10GBE_PRBS_EN 0x08
#define THREEP_10GBE_TX_DBG_PKT 0x40
#define THREEP_10GBE_RX_PRBS 0x80

#define THREEP_P0_RCV_SYNC_CTRL 0x0101008E
#define THREEP_P0_SYNCH_ARM     0x80
#define THREEP_P0_SYNCH_BYTES   0x4
#define THREEP_P0_SRC_1         0

#define THREEP_P1_XMT_FRAMING   0x010100A9
#define THREEP_P2_XMT_FRAMING   0x010100C9
#define RESET_PTR       0x01
#define TEST_DATA       0x02
#define TX_FRAME_EN     0x04
#define EN_SCRAMBLE     0x08

#define THREEP_P1_TX_STATUS     0x010100AA
#define THREEP_P2_TX_STATUS     0x010100AA
#define TX_FRAMED       0x01

#define THREEP_P0_10GBE_LF_STATUS 0x0101008C
#define THREEP_10GBE_LF_MASK    0x03
#define THREEP_10GBE_RT_RXLF    0x10
#define THREEP_10GBE_RT_TXLF    0x20

#define THREEP_P1_B1_ERROR_MASK 0x010100AC
#define THREEP_P1_B2_ERROR_MASK 0x010100CC

#define THREEP_P0_10GBE_LPBK_CTRL 0x0101008D
#define THREEP_10GBE_LPBK_EN 0x01

#define THREEP_P0_10GBE_PCS_CTRL 0x0101008E
#define THREEP_10GBE_DIS_DEC    0x01
#define THREEP_10GBE_DIS_DESCRAM        0x02
#define THREEP_10GBE_DIS_ENC    0x10
#define THREEP_10GBE_DIS_SCRAM  0x20

#define THREEP_P1_RCV_SYNC_CTRL    0x010100AE
#define THREEP_P2_RCV_SYNC_CTRL    0x010100CE

#define THREEP_SYNC_TRIGGER 0x0101008F
#define SYNC_START           0x20

#define THREEP_P0_PRBS_CTRL 0x01010090
#define THREEP_P1_PRBS_CTRL 0x010100B0
#define THREEP_P2_PRBS_CTRL 0x010100C0
#define CH_PRBS_GEN_EN  0x01
#define CH_PRBS_CHK_EN  0x02
#define CH_PRBS_SYNC 0x10
#define CH_PRBS_ERR     0x20
#define CH_PRBS_HLD_ERR 0x40


#define PHY_RST 0x01
#define IDLY_RDY        0x10
#define PLL_LOCK        0x20
#define PHY_INITDONE    0x40


#define THREEP_UNDERFLOW    0x010100F9
#define THREEP_OVERFLOW     0x010100FA
#define RX_P0 0
#define RX_P1 1
#define RX_P2 2
#define TX_P0 4
#define TX_P1 8
#define TX_P2 0x10

#define THREEP_FREQ_CNT_EN      0x010100F4
#define FREQ_CNT_EN_MASK 0x07
#define FREQ_CNT_SEL_MASK 0xF0

#define THREEP_FREQ_CNT 0x030100F5


#define THREEP_MEZZ_STRING      0x010100E0

#define THREEP_BANK0A_CTRL      0x010100E4
#define THREEP_BANK0B_CTRL      0x010100E5
#define THREEP_BANK1_CTRL      0x010100E6


#define THREEP_I2C_DEVICE        0x010100E7
#define THREEP_I2C_READ_ADDRESS  0x010100E8
#define THREEP_I2C_WRITE_ADDRESS 0x010100E9
#define THREEP_I2C_WRITE_DATA    0x010100EA

#define THREEP_PRBS_MODE        0x010100EE

#define THREEP_FREQ_CNT_EN      0x010100F4
#define THREEP_FREQ_CNT_EN_MSK 0x07

#define THREEP_FREQ_CNT 0x030100F5

/* for stm64 */

#define THREEP_P0_FRAMER_RATE   0x01010091

/*
 * device addresses for THREEP_I2C_DEVICE register
 * selects different serial devices
 */
#define THREEP_DEV_XMT_CLK      0  /* SI5326 */
#define THREEP_P0_REF_CLK       1  /* SI570 */
#define THREEP_P1_REF_CLK       2  /* SI570 */
#define THREEP_P2_REF_CLK       3  /* SI570 */
#define THREEP_P0_SFP_EEPROM   4  /* SFP eeprom */
#define THREEP_P0_SFP_DIAG     5  /* SFP diagnostic */
#define THREEP_P1_SFP_EEPROM   6  /* SFP eeprom */
#define THREEP_P1_SFP_DIAG     7  /* SFP diagnostic */
#define THREEP_P2_SFP_EEPROM   8  /* SFP eeprom */
#define THREEP_P2_SFP_DIAG     9  /* SFP diagnostic */
#define THREEP_AMCC            10  /* AMCC MDIO */

#define THREEP_P0_CLOCK_VALUE       155520000.0
#define THREEP_P1_CLOCK_VALUE       155520000.0
#define THREEP_P2_CLOCK_VALUE       155520000.0


/* adt7461 access */

#define THREEP_ADT7461_BASE        0x01010065
/*
 * the AMCC part can be set for 10 G bit ethernet or sdh
 */
#define THREEP_MODE_SDH         STM64_RATE
#define THREEP_MODE_G709        OTU2_RATE
#define THREEP_MODE_10GBE       GIG10E_RATE
#define THREEP_MODE_10P3        3
#define THREEP_MODE_OTU2E       OTU2E_RATE
#define THREEP_MODE_OTU2F       OTU2F_RATE


/* Extended registers */

/* Port 0 STM64 - oc192 port 1 */

#define THREEP_P0_XMIT_PATTERN          EDT_IND_REG_2(0x800001)
#define THREEP_P0_B1_ERROR_CNT          EDT_IND_REG_3(0x800005)
#define THREEP_P0_B2_ERROR_CNT          EDT_IND_REG_4(0x800008)
#define THREEP_P0_M1_ERROR_CNT          EDT_IND_REG_3(0x80000C)
#define THREEP_P0_LOF_CNT                       EDT_IND_REG_2(0x80000F)
#define THREEP_P0_FRM_PAT_CNT           EDT_IND_REG_2(0x800011)
#define THREEP_P0_FALSE_FRM_CNT         EDT_IND_REG_2(0x800013)
#define THREEP_P0_DEMUX_BITMASK         EDT_IND_REG_2(0x800015)
#define THREEP_P0_DEMUX_BITMASK_LO          EDT_IND_REG_1(0x800015)
#define THREEP_P0_DEMUX_BITMASK_HI          EDT_IND_REG_1(0x800016)
#define THREEP_P0_DEMUX_MASK_ADDR           EDT_IND_REG_1(0x800017)
#define THREEP_P0_DEMUX_BITMASK_RD          EDT_IND_REG_2(0x800018)
#define THREEP_P0_DEMUX_BITMASK_RD_LO   EDT_IND_REG_1(0x800018)
#define THREEP_P0_DEMUX_BITMASK_RD_HI   EDT_IND_REG_1(0x800019)

/* Port 1 SDH - like ocm */

#define THREEP_P1_XMIT_NATIONAL         EDT_IND_REG_4(0x800100)
#define THREEP_P1_XMIT_PATTERN          EDT_IND_REG_4(0x800101)
#define THREEP_P1_B1_ERROR_CNT          EDT_IND_REG_3(0x800105)
#define THREEP_P1_B2_ERROR_CNT          EDT_IND_REG_4(0x800108)
#define THREEP_P1_M1_ERROR_CNT          EDT_IND_REG_3(0x80010C)
#define THREEP_P1_LOF_CNT                       EDT_IND_REG_2(0x80010F)
#define THREEP_P1_FRM_PAT_CNT           EDT_IND_REG_2(0x800111)
#define THREEP_P1_FALSE_FRM_CNT         EDT_IND_REG_2(0x800113)
#define THREEP_P1_DEMUX_BITMAP          EDT_IND_REG_1(0x800115)
#define THREEP_P1_DEMUX_BITMAP_RD           EDT_IND_REG_1(0x800116)

/* Port 2 SDH */

#define THREEP_P2_XMIT_NATIONAL         EDT_IND_REG_4(0x800200)
#define THREEP_P2_XMIT_PATTERN          EDT_IND_REG_4(0x800201)
#define THREEP_P2_B1_ERROR_CNT          EDT_IND_REG_3(0x800205)
#define THREEP_P2_B2_ERROR_CNT          EDT_IND_REG_4(0x800208)
#define THREEP_P2_M1_ERROR_CNT          EDT_IND_REG_3(0x80020C)
#define THREEP_P2_LOF_CNT                       EDT_IND_REG_2(0x80020F)
#define THREEP_P2_FRM_PAT_CNT           EDT_IND_REG_2(0x800211)
#define THREEP_P2_FALSE_FRM_CNT         EDT_IND_REG_2(0x800213)
#define THREEP_P2_DEMUX_BITMAP          EDT_IND_REG_1(0x800215)
#define THREEP_P2_DEMUX_BITMAP_RD           EDT_IND_REG_1(0x800216)

typedef struct {
    double ch0_clock_freq; /* ref si570 for ch0 (AMCC/MGT) */ 
    double ch1_clock_freq; /* ref si570 for ch1 (slk2511/MGT) */
    double ch2_clock_freq; /* ref si570 for ch2 (slk2511/MGT) */
    double xmt_clock_freq; /* 10g transmit */
    EdtSI570 ch0_clock_values;
    EdtSI570 ch1_clock_values;
    EdtSI570 ch2_clock_values;
    EdtSI53xx xmt_clock_values;
    int  xmt_clock_source; /* 0 for ref clock, 1 for rcv_clock */
} EdtThreePClocks;

#ifdef __cplusplus
extern "C" {
#endif

EDTAPI int
edt_threep_configure_clks(EdtDev *edt_p, 
                     EdtThreePClocks *clocks);

EDTAPI void
edt_threep_amcc_chk_enable( EdtDev * edt_p, int mode);
EDTAPI void
edt_threep_amcc_local_loop( EdtDev * edt_p, int set);
EDTAPI void
edt_threep_amcc_remote_loop( EdtDev * edt_p, int set);
EDTAPI void
edt_threep_amcc_set_tx_prbs( EdtDev * edt_p, int code);
EDTAPI void
dump_threep_freq_cntrs( EdtDev * edt_p, int en);
EDTAPI int 
edt_threep_amcc_clk_mode(double freq);


EDTAPI int
edt_threep_si5326_dump(EdtDev *edt_p, int device);
EDTAPI int
edt_threep_si5326_load_array(EdtDev *edt_p,  Edt2WireRegArray *vec, int device);
EDTAPI void
edt_threep_amcc_config_tx( EdtDev * edt_p, int mode);
EDTAPI void
edt_threep_amcc_config_rx( EdtDev * edt_p, int mode);
EDTAPI int
edt_threep_configure_clock(EdtDev *edt_p, double frequency, int port, 
                            EdtSI570 * clock_values);

EDTAPI unsigned char
edt_threep_amcc_reg_read( EdtDev * edt_p, u_int address);
EDTAPI unsigned char
edt_threep_amcc_reg_set_bits( EdtDev * edt_p, u_int address, u_int value, 
                             u_int shift, u_int mask);

EDTAPI uint_t
edt_3p_mn_ser_dev_reg_write(EdtDev * edt_p, 
                            uint_t base_desc,
                            uint_t device_id,
                            uint_t address, 
                            uint_t value);

EDTAPI uint_t
edt_3p_mn_ser_dev_reg_read(EdtDev * edt_p, 
                           uint_t base_desc, 
                           uint_t device_id,
                           uint_t address,
                           uint_t* bytes);
EDTAPI uint_t
edt_3p_adt7461_reg_read(EdtDev * edt_p, 
                        uint_t base_desc, 
                        uint_t device_id,
                        uint_t address,
                        uint_t* bytes);
EDTAPI uint_t
edt_3p_adt7461_reg_write(EdtDev * edt_p, 
                         uint_t base_desc, 
                         uint_t device_id,
                         uint_t address,
                         uint_t value);

EDTAPI double edt_3p_v6_temp(EdtDev *edt_p);


#ifdef __cplusplus
}
#endif

#endif

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