00001
00002 #ifndef EDT_VCO_H
00003 #define EDT_VCO_H
00004
00005 #define SSD_REF_XTAL 10000000.0
00006 #define XTAL20 10000000.0
00007 #define XTAL40 20000000.0
00008 #define XTAL60 30000000.0
00009 #define LOW_REF 225000.0
00010 #define HI_REF 5000000.0
00011 #define LOW_VCO 50000000.0
00012 #define HI_VCO 250000000.0
00013 #define F_XILINX 100000000.0
00014
00015
00016
00017 #define F_LOW 30000000.0
00018
00019
00020 #define F_SS_LOW 120000000.0
00021
00022
00023 #define F_XILINX_307 200000000.0
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 EDTAPI
00029 double
00030 edt_find_vco_frequency(EdtDev *edt_p, double target, double xtal,
00031 edt_pll *pll, int verbose);
00032 EDTAPI
00033 void
00034 edt_set_pll_clock(EdtDev *edt_p, int ref_xtal, edt_pll *clkset, int verbose);
00035
00036
00037 #define RDW m
00038 #define VDW n
00039 #define OD v
00040
00041
00042 EDTAPI
00043 double
00044 edt_find_vco_frequency_ics307(EdtDev *edt_p, double target,
00045 double xtal, edt_pll *pll, int verbose);
00046
00047 EDTAPI
00048 double
00049 edt_find_vco_frequency_ics307_nodivide(EdtDev *edt_p, double target,
00050 double xtal, edt_pll *pll, int verbose);
00051
00052 EDTAPI
00053 double
00054 edt_set_frequency_ics307(EdtDev *edt_p,
00055 double ref_xtal,
00056 double target,
00057 int clock_channel,
00058 int finaldivide);
00059
00060 EDTAPI
00061 void
00062 edt_set_out_clk_ics307(EdtDev * edt_p, edt_pll * clk_data, int clock_channel);
00063
00064
00065 #ifdef __cplusplus
00066 }
00067 #endif
00068
00069 #endif
00070
00071