PCIe8 G3 A5-40G
The PCIe8g3 A5-40G is a fast, versatile low-profile PCI Express (PCIe, Gen3) x8 interface, available with either a full or a half-height back panel. It has one 40G QSFP+ port and supports 40GbE or OTU3.
The port, which has its own reference clock programmable for 1–808 MHz., links to the FPGA for serialization / deserialization (SERDES) and clock recovery.
The FPGA is an Altera Arria V GZ (E3, E5, or E7) with access to one 64-bit wide 2 GB block of DRAM (DDR3), which can act as a data buffer. The FPGA provides up to 8 independent DMA channels via EDT FPGA configuration files.
A time code input (1 pps or IRIG-B) also is included, with an option for either DB9 or BNC cabling.
EDT FPGA configuration files are included to support 40GbE (at the PCS and PMA layers) and OTU3 (raw, framed, framed and descrambled).
Custom files can be requested.