cl_logic_lib.c File Reference

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Detailed Description

Library routines for parsing parsing c-link logic analyzer output; depends on EDT c-link logic analyzer FPGA loaded into the board (for example camlkla_xx.bit).

Definition in file cl_logic_lib.c.

#include <stdio.h>
#include <string.h>
#include "edtinc.h"
#include "cl_logic_lib.h"
#include "pciload.h"

Go to the source code of this file.

Defines
#define	CL_LOGIC_FRAME_GRAN   256
#define	CLOCKS(v)   (((v) & CLOCK_MASK)+1)
#define	DV(v)   (v & DV_MASK)
#define	FLAGS(v, testmask)   (v & testmask)
#define	FV(v)   (v & FV_MASK)
#define	LV(v)   (v & LV_MASK)
Functions
void	cl_logic_stat_add (ClLogicStat *clp, int value)
	cl_logic_stat_clear (ClLogicStat *clp)
void	cl_logic_stat_print (char *label, ClLogicStat *clp, double clockspeed, int verbose)
int	cl_logic_stats_neq (ClLogicStat *clp1, ClLogicStat *clp2)
void	cl_logic_summary_add_frame (ClLogicSummary *clp, int width, int height, int hblank, int vblank)
void	cl_logic_summary_init (ClLogicSummary *cls_p, int testmask, int numbufs, int bufsize, int timeout, double pixel_clock)
u_int	edt_read_pci_config (EdtDev *edt_p, int addr)
void	edt_reboot_pci (EdtDev *edt_p, int verbose)
void	edt_write_pci_config (EdtDev *edt_p, int addr, int value)
size_t	get_buffer_card (unsigned short *buffer, int size, PdvDev *f)
size_t	get_buffer_file (unsigned short *buffer, int size, FILE *f)
size_t	get_next_logic_buffer (unsigned short *buffer, int size, PdvDev *pdv_p, FILE *f)
int	pdv_cl_logic_sample (PdvDev *pdv_p, FILE *f, ClLogicSummary *clsp, int verbose, int quiet, int load, char *outfilename, unsigned int loops, int timeout, int max_timeouts)

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