lib_e3t3.c

/* #pragma ident "@(#)lib_e3t3.c        1.8 06/02/11 EDT" */

#include <stdio.h>
#include <math.h>

#include <string.h>

#include <stdlib.h>

#include "edtinc.h"

#include "edt_vco.h"
#include "edt_ss_vco.h"

#include "lib_e3t3.h"

#include "edt_bitload.h"

#define E3FREQ  34368000.0
#define T3FREQ  44736000.0
#define XTAL    10368100.0

/*
* offsets in the 8 bit indirect space 78P2344JAT serial pins
*/
#define TDK78P2344_EN_D         0x0101004A
#define TDK78P2344_EN_D_0       0x0101004A
#define TDK78P2344_EN_D_1       0x0101004B      
#define TDK78P2344_CTL  0x0101004C
#define TDK78P2344_LOS  0x01010048

#define TDK78P2344_LOS_0        0x01010045
#define TDK78P2344_LOS_1        0x01010046
#define TDK78P2344_LOS_2        0x01010047
#define TDK78P2344_LOS_3        0x01010048

/* bits in the data enable register */
#define TDK78P2344_ENCH 0xff

/* bits in the control register for c3 board*/

#define TDK78P2344_C3_EN_TX 0x0f

/* bits in the control register for 16te3 board*/
#define TDK78P2344_16TE3_SEL_0 0x00
#define TDK78P2344_16TE3_SEL_1 0x01
#define TDK78P2344_16TE3_SEL_2 0x02
#define TDK78P2344_16TE3_SEL_3 0x03

/* bits common to both */

#define TDK78P2344_ENABLE 0x10
#define TDK78P2344_SDI  0x20
#define TDK78P2344_SCK  0x40
#define TDK78P2344_CS   0x80

/* bits in the status register */
#define TDK78P2344_INTR 0x0f

/* unfortunately SDO bit is not the same on c3/16te3 */

#define TDK78P2344_16TE3_SDO    0x10
#define TDK78P2344_C3_SDO       0x20

/* Page bamks in the TDK78P2344 */
#define GLOBAL_BANK     0x0
#define CHAN_BANK_BASE  0x1

/* sub addresses in the global bank */
#define TDK78P2344_MSCR 0x0
#define TDK78P2344_INTC 0x1

/* sub addresses in each per port bank */
#define TDK78P2344_MDCR 0x0
#define TDK78P2344_STAT 0x1
#define TDK78P2344_JACR 0x3


void
edt_write_78P2344_s_bit(EdtDev * edt_p, u_int bit)
{
    /* assume the sck  and sdi are low  */
    /* always set serial enable (CS) */
    if (bit == 0)
    {
        edt_reg_or( edt_p, TDK78P2344_CTL, TDK78P2344_CS );
    }
    else
    {
        edt_reg_or( edt_p, TDK78P2344_CTL, TDK78P2344_CS | TDK78P2344_SDI );
    }
    /* set sck */
    edt_reg_or( edt_p, TDK78P2344_CTL, TDK78P2344_SCK );
    /* clear sdi and sck together (data is latched on the rising edge */
    edt_reg_and(edt_p, TDK78P2344_CTL, ~(TDK78P2344_SDI | TDK78P2344_SCK));

    edt_reg_read(edt_p, TDK78P2344_CTL);

}

u_int
edt_read_78P2344_s_bit(EdtDev * edt_p, u_int los, u_int sdo)
{
    volatile u_int tdk_stat;
    /* read the first bit before clocking to the next */
    tdk_stat = edt_reg_read(edt_p, los);
    /* assume SCK is low to start - always set serial enable high */
    edt_reg_or( edt_p, TDK78P2344_CTL, TDK78P2344_CS | TDK78P2344_SCK );
    edt_reg_and(edt_p, TDK78P2344_CTL, ~(TDK78P2344_SDI | TDK78P2344_SCK));
    if ((tdk_stat & sdo) == 0)
    {
        return(0);
    }
    else
    {
        return(1);
    }
}

void
edt_78p2344_serial_add(EdtDev * edt_p, u_int bank, u_int sub_add)
{
    volatile int i;

    /* read write bit is already sent */
    for(i=0; i<3; i++)
    {
        edt_write_78P2344_s_bit(edt_p, (sub_add & 0x1));
        sub_add >>= 1;
    }
    for(i=0; i<4; i++)
    {
        edt_write_78P2344_s_bit(edt_p, (bank & 0x1));
        bank >>= 1;
    }
}

unsigned char
edt_read_78p2344_reg(EdtDev * edt_p, u_int bank, u_int sub_add, u_int los, u_int sdo)
{
    int i;
    volatile unsigned char data = 0;

    /* output read/write bit as 1 (read) */
    edt_write_78P2344_s_bit(edt_p, 1);
    /* output address */
    edt_78p2344_serial_add(edt_p, bank, sub_add);
    for(i=0; i<8; i++)
    {
        data >>= 1;
        if ( (edt_read_78P2344_s_bit(edt_p, los, sdo)) != 0)
        {
            data |= 0x80;
        }
    }
    /* drop serial enable */
    edt_reg_and(edt_p, TDK78P2344_CTL, ~(TDK78P2344_CS));
    return(data);
}

void
edt_write_78p2344_reg(EdtDev * edt_p, u_int bank, u_int sub_add, unsigned char indata)
{
    volatile int i;
    volatile int data = indata;
    /* output read/write bit as 0 (write) */
    edt_write_78P2344_s_bit(edt_p, 0);
    /* output address */
    edt_78p2344_serial_add(edt_p, bank, sub_add);
    for(i=0; i<8; i++)
    {
        edt_write_78P2344_s_bit(edt_p, (data & 0x1));
        data >>= 1;
    }
    /* drop serial enable */
    edt_reg_and(edt_p, TDK78P2344_CTL, ~(TDK78P2344_CS));

    {
        volatile u_int los;
        volatile u_int sdo;
        volatile u_int chip = edt_reg_read(edt_p,  TDK78P2344_CTL) & 0x3;
        volatile u_int readback;
        if (edt_is_combo3(edt_p->mezz.id))
        {
            los =  TDK78P2344_LOS;
            sdo =  TDK78P2344_C3_SDO;
        }
        else if (edt_p->mezz.id == MEZZ_16TE3)
        {
            los =  TDK78P2344_LOS_0 + chip;
            sdo =  TDK78P2344_16TE3_SDO;        
        } else {
            edt_msg(EDTLIB_MSG_WARNING, "edt_write_78p2344_reg: ERROR, invalid mezz.id (0x%x)\n",
                edt_p->mezz.id);
            return;
        }


        readback = edt_read_78p2344_reg(edt_p, bank, sub_add, los, sdo);

        if (readback != indata)
        {
            edt_msg(EDTLIB_MSG_WARNING, "data not set correctly %02x != %02x\n", readback, indata);
        }

    }

}



void
edt_tdk78P2344_e3t3_init(EdtDev *edt_p, int loopback, int transmit, u_int mscr)
{
    volatile int i;
    volatile u_int los;
    volatile u_int sdo;
    volatile u_int chip = edt_reg_read(edt_p,  TDK78P2344_CTL) & 0x3;
    volatile u_int readback;

    if (edt_is_combo3(edt_p->mezz.id))
    {
        los =  TDK78P2344_LOS;
        sdo =  TDK78P2344_C3_SDO;
    }
    else if (edt_p->mezz.id == MEZZ_16TE3)
    {
        los =  TDK78P2344_LOS_0 + chip;
        sdo =  TDK78P2344_16TE3_SDO;

    } else {
        edt_msg(EDTLIB_MSG_WARNING, "edt_tdk78P2344_e3t3_init: ERROR, invalid mezz.id (0x%x)\n",
            edt_p->mezz.id);
        return;
    }

    edt_write_78P2344_s_bit(edt_p, 1);
    /* set glogal register 0 for e3, endec on and sense on falling edge */

    edt_write_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, mscr);
    readback = edt_read_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, los, sdo);
    edt_write_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, mscr);
    readback = edt_read_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, los, sdo);

    edt_msg(EDTLIB_MSG_INFO_2, "MSCR set %02x read %02x\n", mscr, readback);

    edt_write_78p2344_reg(edt_p, 0, TDK78P2344_INTC, 0x82); /* intr is los */
    /* for each channel */
    for(i=0; i<4; i++)
    {
        if ((loopback & (0x1 << i)) == 0)
            if ((transmit & (0x1 << i)) != 0)
                edt_write_78p2344_reg(edt_p, i+1, TDK78P2344_MDCR, 0x21);
            else
                edt_write_78p2344_reg(edt_p, i+1, TDK78P2344_MDCR, 0x20);
        else
            edt_write_78p2344_reg(edt_p, i+1, TDK78P2344_MDCR, 0x29);

        edt_write_78p2344_reg(edt_p, i+1, TDK78P2344_JACR, 0x8c);
    }
}

void
edt_tdk78P2344_dump(EdtDev *edt_p, int chip)
{
    volatile int i;
    volatile u_int los;
    volatile u_int sdo;

    if (edt_is_combo3(edt_p->mezz.id))
    {
        los =  TDK78P2344_LOS;
        sdo =  TDK78P2344_C3_SDO;
    }
    else if (edt_p->mezz.id == MEZZ_16TE3)
    {
        los =  TDK78P2344_LOS_0 + chip;
        sdo =  TDK78P2344_16TE3_SDO;

    }
    else
    {
        edt_msg(EDTLIB_MSG_WARNING, "edt_tdk78P2344_dump requires setting edt_p->mezz.id\n");
        return;
    }

    if (edt_p->mezz.id == MEZZ_16TE3)
        printf("78P2344 Chip %d, Chan %2d-%2d, ", chip, chip *4, (chip *4) + 3);

    printf("Global registers: MSCR = %02x ", 
        edt_read_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, los, sdo));
    printf("INTC = %02x\n", edt_read_78p2344_reg(edt_p, 0, TDK78P2344_INTC, los, sdo));
    /* for each channel */
    for(i=0; i<4; i++)
    {
        printf("\tChannel %d registers: MDCR = %02x ", i, 
            edt_read_78p2344_reg(edt_p, i+1, TDK78P2344_MDCR, los, sdo));
        printf("STAT = %02x ", edt_read_78p2344_reg(edt_p, i+1, TDK78P2344_STAT, los, sdo));
        printf("JACR = %02x\n", edt_read_78p2344_reg(edt_p, i+1, TDK78P2344_JACR, los, sdo));
    }
}

void
edt_c3_set_direction_switch(EdtDev *edt_p, int transmit)

{
    /* unreset tdk  set relay direction */
    volatile u_char ctl;

    ctl = edt_reg_read(edt_p, TDK78P2344_CTL) & ~TDK78P2344_C3_EN_TX;

    edt_reg_write(edt_p, TDK78P2344_CTL, 
        ctl | (TDK78P2344_C3_EN_TX & transmit)); 

}

void
edt_setup_c3_e3t3(EdtDev *edt_p, int reset, int transmit, int loopback, int t3)

{
    volatile double target = E3FREQ;
    volatile u_int mscr = 0xAC;

    if (t3)
    {
        target = T3FREQ;
        mscr   = 0xCC;
    }

    /* reset tdk78p2344 and the turn off data */
    edt_reg_write(edt_p, TDK78P2344_CTL, 0);

    if (reset == 1)
    {
        /* hardware reset lxt3108 and the rest of the interface chip */
        edt_reg_write(edt_p, PCD_CMD, 0);

        edt_msleep(1); /* reset low for a while */
        /* unreset chip and lxt3108 */
        edt_reg_write(edt_p, PCD_CMD, 0x8);
    }

    /*  set pll 2 for e3 clock times 1 */

    edt_set_frequency_ics307(edt_p, XTAL, target, 2, 0);

    /* unreset tdk  set relay direction */
    edt_reg_write(edt_p, TDK78P2344_CTL, 
        TDK78P2344_ENABLE | (TDK78P2344_C3_EN_TX & (transmit | loopback))); 
    edt_reg_read(edt_p, TDK78P2344_CTL);


    /* enable the data */
    edt_reg_write(edt_p, TDK78P2344_EN_D, TDK78P2344_ENCH); 
    edt_reg_read(edt_p, TDK78P2344_EN_D);


    edt_tdk78P2344_e3t3_init(edt_p, loopback, transmit, mscr);

}

void
edt_16te3_set_chip(EdtDev *edt_p, int chip)

{
    edt_reg_write(edt_p, TDK78P2344_CTL, 
        TDK78P2344_ENABLE | chip);
}

void
edt_setup_16te3_e3t3(EdtDev *edt_p, int reset, int transmit, int loopback, int t3)

{
    volatile double target = E3FREQ;
    volatile u_int mscr = 0xAC;
    volatile int chip;

    if (t3)
    {
        target = T3FREQ;
        mscr   = 0xCC;
    }

    /* reset tdk78p2344 and the turn off data */
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_0);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_1);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_2);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_3);

    if (reset == 1)
    {
        /* hardware reset lxt3108 and the rest of the interface chip */
        edt_reg_write(edt_p, PCD_CMD, 0);

        edt_msleep(1); /* reset low for a while */
        /* unreset chip and lxt3108 */
        edt_reg_write(edt_p, PCD_CMD, 0x8);
    }

    /*  set pll 2 for e3 clock times 1 */

    edt_set_frequency_ics307(edt_p, XTAL, target, 2, 0);

    /* unreset tdk  set relay direction */
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_0);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_ENABLE); 

    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_1);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_ENABLE); 

    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_2);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_ENABLE); 

    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_3);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_ENABLE); 


    /* enable the data */
    edt_msleep(10);
    edt_reg_write(edt_p, TDK78P2344_EN_D_0, TDK78P2344_ENCH); 
    edt_msleep(10);
    edt_reg_write(edt_p, TDK78P2344_EN_D_1, TDK78P2344_ENCH); 
    edt_msleep(10);


    for (chip = 0; chip < 4; chip++)
    {
        edt_16te3_set_chip(edt_p, chip);
        edt_tdk78P2344_e3t3_init(edt_p, loopback, transmit, mscr);
    }
}


/* Defines for testing 16TE3 boards w/no cpld programming */
#define TDK78P2344_EN_D_0       0x0101004A
#define TDK78P2344_EN_D_1       0x0101004B      
#define TDK78P2344_LOS_0        0x01010045
#define TDK78P2344_CTL          0x0101004C
#define TDK78P2344_ENABLE       0x10
#define TDK78P2344_ENCH         0xff
#define TDK78P2344_16TE3_SEL_3  0x03
#define TDK78P2344_16TE3_SDO    0x10
#define TDK78P2344_MSCR         0x0
#define TDK78P2344_MDCR         0x0

int
edt_test_16te3(EdtDev *edt_p)

{
    int rc;

    /* If here test for 16te3 mezzanine board with cpld's not programmed. */
    u_int los, sdo, mscr, mdcr;

    puts("Testing for 16TE3 with unprogrammed CPLD:  Loading te3_16io_test.bit");
    if ((rc = edt_bitload(edt_p, NULL, "te3_16io_test.bit", 0, 0)) != 0)
    {
        edt_msg(EDTLIB_MSG_WARNING, "Unable to load %s\n", "te3_16io_test.bit");
        return -1;
    }
    edt_intfc_write(edt_p, PCD_CMD, 0x08); /* Enable the UI Xilinx */
    edt_intfc_write(edt_p, 2, 0x00);       /* Enable the 16TE3 LIU output ports */


    /* reset tdk78p2344 and the turn off data */
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_3);


    /* hardware reset lxt3108 and the rest of the interface chip */
    edt_reg_write(edt_p, PCD_CMD, 0);
    edt_msleep(1); /* reset low for a while */
    /* unreset chip and lxt3108 */
    edt_reg_write(edt_p, PCD_CMD, 0x8);


    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_16TE3_SEL_3);
    edt_reg_write(edt_p, TDK78P2344_CTL, TDK78P2344_ENABLE); 


    /* enable the data */
    edt_reg_write(edt_p, TDK78P2344_EN_D_0, TDK78P2344_ENCH); 
    edt_reg_write(edt_p, TDK78P2344_EN_D_1, TDK78P2344_ENCH); 


    los =  TDK78P2344_LOS_0 + 3;
    sdo =  TDK78P2344_16TE3_SDO;

    edt_16te3_set_chip(edt_p, 3);

    mscr = edt_read_78p2344_reg(edt_p, 0, TDK78P2344_MSCR, los, sdo);

    mdcr = edt_read_78p2344_reg(edt_p, 3+1, TDK78P2344_MDCR, los, sdo);

    if (mscr = 0x20 && mdcr == 0x21)
    {
        return 1;
    }

    return 0;

}

---