lib_threep.c

/* #pragma ident "@(#)set_ss_vco.c      1.17 01/17/05 EDT" */

#include <stdio.h>
#include <math.h>

#include <string.h>

#include <stdlib.h>

#include "edtinc.h"

#include <stddef.h>

#include "edt_si5326.h"


#include "edt_threep.h"

#include "edt_ocm.h"

#include "lib_two_wire.h"

static
Edt2WireRegArray threep_15552[EDT_SI5326_NREGS+1] = {
    //FROM net10g//
    {  0,0x14},
    {  1,0xe4},
    {  2,0xa2},
    {  3,0x5},
    {  4,0x92},
    {  5,0xed},
    {  6,0x2d},
    {  7,0x2a},
    {  8,0x0},
    {  9,0xc0},
    { 10,0x8},
    { 11,0x48},
    { 16,0x0},
    { 17,0x80},
    { 18,0x0},
    { 19,0x29},
    { 20,0x3e},
    { 21,0xff},
    { 22,0xdf},
    { 23,0x1f},
    { 24,0x3f},
    { 25,0x80},
    { 31,0x0},
    { 32,0x0},
    { 33,0x3},
    { 34,0x0},
    { 35,0x0},
    { 36,0x3},
    { 40,0x80},
    { 41,0x1},
    { 42,0x37},
    { 43,0x0},
    { 44,0x0},
    { 45,0x4d},
    { 46,0x0},
    { 47,0x0},
    { 48,0x4d},
    { 55,0x0},
    {131,0x1f},
    {132,0x2},
    {136,0x40},
    {142,0x0},
    {143,0x0},
    {256,0}
};

Edt2WireRegArray threep_16113[EDT_SI5326_NREGS+1] = {
    //try for 161Mhz clk//
    {  0,0x14},
    {  1,0xe4},
    {  2,0xa2},
    {  3,0x15},
    {  4,0x92},
    {  5,0xed},
    {  6,0x3e}, //{  6,0x2d}, //LVPECL outputs
    {  7,0x2a},
    {  8,0x0},
    {  9,0xc0},
    { 10,0x0},
    { 11,0x40},
    { 16,0x0},
    { 17,0x80},
    { 18,0x0},
    { 19,0x2c},
    { 20,0x3e},
    { 21,0xff},
    { 22,0xdf},
    { 23,0x1f},
    { 24,0x3f},
    { 25,0x0},
    { 31,0x0},
    { 32,0x0},
    { 33,0x7},
    { 34,0x0},
    { 35,0x0},
    { 36,0x7},
    { 40,0x40},
    { 41,0x1},
    { 42,0xaf},
    { 43,0x0},
    { 44,0x0},
    { 45,0x50},
    { 46,0x0},
    { 47,0x0},
    { 48,0x50},
    { 55,0x0},
    {131,0x1f},
    {132,0x2},
    {136,0x40},
    {138,0xf},
    {139,0xff},
    {142,0x0},
    {143,0x0},
    {256,0}
};

/*
* Net10g AMCC S19250 10G Serdes is written and read as a serial device like
* the clocks and transceivers. It has 256 register address space but the MDIO
* interface can only address 64 registers at a time. The part implements a page
* scheme which is always in register 0 of each page. The top three bits of
* the page register are the top three bits of the 8 bit register address.
* We will always write the page register for each register access.
* The AMCC part has many reserved bits that must be preserved on writes. 
* The part will always be written with a "set_bits" routine to preserve
* uneffected bits.
*/
unsigned char
edt_threep_amcc_reg_read( EdtDev * edt_p, u_int address)
{
    unsigned char byte;
    edt_serial_dev_set_bits(edt_p, THREEP_I2C_DEVICE, THREEP_AMCC,
        EDT_AMCC_S19250_PAGE, address,  0, EDT_AMCC_S19250_PAGE_MASK);
    byte = edt_serial_dev_reg_read(edt_p, THREEP_I2C_DEVICE, THREEP_AMCC,
        address & ~EDT_AMCC_S19250_PAGE_MASK);
    return(byte);
}

unsigned char
edt_threep_amcc_reg_set_bits( EdtDev * edt_p, u_int address, u_int value, u_int shift, u_int mask)
{
    unsigned char byte;

    /* set the page register */
    edt_serial_dev_set_bits(edt_p, THREEP_I2C_DEVICE, THREEP_AMCC,
        EDT_AMCC_S19250_PAGE, address,  0, EDT_AMCC_S19250_PAGE_MASK);
    /* set the register and return last value */
    byte = edt_serial_dev_set_bits(edt_p, THREEP_I2C_DEVICE, THREEP_AMCC,
        address & ~EDT_AMCC_S19250_PAGE_MASK, value, shift, mask);
    return(byte);
}

/*
* set AMCC transmit  for divide by 16 mode
* then reset the tx
* call this after the transmit clock chips have been set for selected clock
*/
void
edt_threep_amcc_config_tx( EdtDev * edt_p, int mode)
{
    int byte;
    int loop = 0;
    int verbose = edt_msg_get_level(edt_msg_default_handle()) &
        EDTLIB_MSG_INFO_1;

    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_79, 0, 0, EDT_AMCC_S19250_TXREFSEL);
    byte = edt_threep_amcc_reg_read( edt_p, EDT_AMCC_S19250_ADDR_79);
    /*
    printf("read 0x79 = %02x\n", byte);
    */

    switch(mode)
    {
    case THREEP_MODE_10P3:
        /* THREEP_MODE_10P3 is a more generalized version of THREEP_MODE_10GBE.
        * It operates at the same VCO frequency, but uses a refclk*64 instead
        * refclk*66 to achieve the VCO frequency.
        */
    case THREEP_MODE_10GBE:
        /* Set up for 10.3125 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_TX_VCO_RNG_10GBER, 0, EDT_AMCC_S19250_TX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_98,
            EDT_AMCC_S19250_TX_VCO_RES_10GBER, 0, EDT_AMCC_S19250_TX_VCO_RES_MASK);
        /* TAP2 CONTROL */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_0C,
            EDT_AMCC_S19250_TAP2_10GBER, 0, EDT_AMCC_S19250_TAP2_CNTL_MASK);
        if (verbose)
            printf("Setting AMCC S19520 TX VCO for 10.3125 Gbps range.\n");
        break;
    case THREEP_MODE_SDH:
        /* Set up for 9.95328 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_TX_VCO_RNG_SDH, 0, EDT_AMCC_S19250_TX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_98,
            EDT_AMCC_S19250_TX_VCO_RES_SDH, 0, EDT_AMCC_S19250_TX_VCO_RES_MASK);
        /* TAP2 CONTROL */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_0C,
            EDT_AMCC_S19250_TAP2_SDH, 0, EDT_AMCC_S19250_TAP2_CNTL_MASK);
        if (verbose)
            printf("Setting AMCC S19520 TX VCO for 9.95328 Gbps range.\n");
        break;
    case THREEP_MODE_G709:
        /* Set up for 10.709225316456 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_TX_VCO_RNG_G709, 0, EDT_AMCC_S19250_TX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_98,
            EDT_AMCC_S19250_TX_VCO_RES_G709, 0, EDT_AMCC_S19250_TX_VCO_RES_MASK);
        /* TAP2 CONTROL */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_0C,
            EDT_AMCC_S19250_TAP2_G709, 0, EDT_AMCC_S19250_TAP2_CNTL_MASK);
        if (verbose)
            printf("Setting AMCC S19520 TX VCO for 10.709 Gbps range.\n");
        break;
    case THREEP_MODE_OTU2E:
        /* Set up for 11.095727848101 Gbps */
    case THREEP_MODE_OTU2F:
    case OTU1E_RATE:

        /* Set up for 11.317642405063 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_TX_VCO_RNG_11P3, 0, EDT_AMCC_S19250_TX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_98,
            EDT_AMCC_S19250_TX_VCO_RES_11P3, 0, EDT_AMCC_S19250_TX_VCO_RES_MASK);
        /* TAP2 CONTROL */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_0C,
            EDT_AMCC_S19250_TAP2_11P3, 0, EDT_AMCC_S19250_TAP2_CNTL_MASK);
        if (verbose)
            printf("Setting AMCC S19520 TX VCO for 11.0957 Gbps range.\n");
        break;
    default:
        edt_perror("edt_threep_amcc_config_tx: invalid mode");
    }
    /*
    byte = edt_threep_amcc_reg_read(edt_p, 0x81);
    printf("AMCC reg 0x81 = 0x%02x\n", byte);
    byte = edt_threep_amcc_reg_read(edt_p, 0x98);
    printf("AMCC reg 0x98 = 0x%02x\n", byte);
    byte = edt_threep_amcc_reg_read(edt_p, 0x0c);
    printf("AMCC reg 0x0c = 0x%02x\n", byte);
    */

    /* reset the transmit section */
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_06, 0, 0, EDT_AMCC_S19250_TX_RSTB);
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_06, EDT_AMCC_S19250_TX_RSTB,
        0, EDT_AMCC_S19250_TX_RSTB);
    byte = edt_reg_read( edt_p, THREEP_P0_LIU_STATUS);
    /*
    printf("read lock stat after rstb = %02x\n", byte);
    */
    byte = edt_threep_amcc_reg_read( edt_p, EDT_AMCC_S19250_ADDR_06);
    /*
    printf("read amcc 0x06 = %02x\n", byte);
    printf("wait for tx_lockdet\n");
    */
    while (((byte = edt_reg_read( edt_p, THREEP_P0_LIU_STATUS)) & TX_LOCKDET) == 0)
        loop++;
    /*
    printf("lock detected %02x in spartan 3 after %d loops\n", byte, loop);
    */
    byte = edt_threep_amcc_reg_read( edt_p, EDT_AMCC_S19250_ADDR_82);
    /*
    printf("read amcc 0x82 = %02x\n", byte);
    */
    byte = edt_threep_amcc_reg_read( edt_p, EDT_AMCC_S19250_ADDR_82);
    /*
    printf("2nd read amcc 0x82 = %02x\n", byte);
    */
    byte = edt_reg_read( edt_p, THREEP_P0_ENABLE); //TODO:SB
    /*
    printf("read dcm stat before = %02x\n", byte);
    */
    edt_reg_write(edt_p, THREEP_P0_ENABLE, byte & ~TXPLL_EN);
    byte = edt_reg_read( edt_p, THREEP_P0_ENABLE); //TODO:SB
    /*
    printf("read dcm stat before = %02x\n", byte);
    */
    edt_msleep(1);
    edt_reg_or( edt_p, THREEP_P0_ENABLE, TXPLL_EN);
    byte = edt_reg_read( edt_p, THREEP_P0_ENABLE);
    /*
    printf("read port 0 enable stat = %02x\n", byte);
    */

    loop = 0;
    while (((byte = edt_reg_read( edt_p, THREEP_P0_ENABLE)) & THREEP_TX_LOCKED) == 0)
        loop++;
    /*
    printf("tx dcm lock detected %02x after %d loops\n", byte, loop);
    */
}

/*
* set AMCC receive clock rate and the AMCC mode (SDH, G.709, 10GBE, OTU2e)
* then reset the rx
* call this after the receive clock chips have been set for selected clock
*/
void
edt_threep_amcc_config_rx( EdtDev * edt_p, int mode)
{
    int verbose = edt_msg_get_level(edt_msg_default_handle()) &
        EDTLIB_MSG_INFO_1;
    /* reset rx rate sel bit to divide by 16 mode */
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, 0, 0, EDT_AMCC_S19250_RX622SEL);
    switch(mode)
    {
    case THREEP_MODE_10GBE:
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, 0, 0, EDT_AMCC_S19250_SONET_RATESEL);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, EDT_AMCC_S19250_GBE_RATE_SEL,
            0, EDT_AMCC_S19250_GBE_RATE_SEL);
        /* Set up for 10.3125 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_RX_VCO_RNG_10GBER, 0, EDT_AMCC_S19250_RX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_94,
            EDT_AMCC_S19250_RX_VCO_RES_10GBER, 0, EDT_AMCC_S19250_RX_VCO_RES_MASK);
        /* PAEQ_LINKOPT1 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1C,
            EDT_AMCC_S19250_PAEQ_LINKOPT1_10GBER , 0, EDT_AMCC_S19250_PAEQ_LINKOPT1_MASK);
        /* PAEQ_LINKOPT2 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1E,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_10GBER, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_MASK);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1F,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_10GBER, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_MASK);
        if (verbose)
        {
            printf("Setting AMCC S19520 RX for 10.3125 Gbps range.\n");
            printf("Setting AMCC S19520 for GBE_RATE_SEL (refclk*66).\n");
        }
        break;
    case THREEP_MODE_SDH:
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, 0,
            0, EDT_AMCC_S19250_GBE_RATE_SEL);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, EDT_AMCC_S19250_SONET_RATESEL,
            0, EDT_AMCC_S19250_SONET_RATESEL);
        /* Set up for 9.95328 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_RX_VCO_RNG_SDH, 0, EDT_AMCC_S19250_RX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_94,
            EDT_AMCC_S19250_RX_VCO_RES_SDH, 0, EDT_AMCC_S19250_RX_VCO_RES_MASK);
        /* PAEQ_LINKOPT1 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1C,
            EDT_AMCC_S19250_PAEQ_LINKOPT1_SDH, 0, EDT_AMCC_S19250_PAEQ_LINKOPT1_MASK);
        /* PAEQ_LINKOPT2 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1E,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_SDH, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_MASK);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1F,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_SDH, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_MASK);
        if (verbose)
        {
            printf("Setting AMCC S19520 RX for 9.95328 Gbps range.\n");
            printf("Setting AMCC S19520 for SONET_RATE_SEL (refclk*64).\n");
        }
        break;
    case THREEP_MODE_G709:
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, 0,
            0, EDT_AMCC_S19250_GBE_RATE_SEL);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, EDT_AMCC_S19250_SONET_RATESEL,
            0, EDT_AMCC_S19250_SONET_RATESEL);
        /* Set up for 10.709225316456 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_RX_VCO_RNG_G709, 0, EDT_AMCC_S19250_RX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_94,
            EDT_AMCC_S19250_RX_VCO_RES_G709, 0, EDT_AMCC_S19250_RX_VCO_RES_MASK);
        /* PAEQ_LINKOPT1 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1C,
            EDT_AMCC_S19250_PAEQ_LINKOPT1_G709, 0, EDT_AMCC_S19250_PAEQ_LINKOPT1_MASK);
        /* PAEQ_LINKOPT2 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1E,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_G709, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_MASK);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1F,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_G709, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_MASK);
        if (verbose)
        {
            printf("Setting AMCC S19520 RX VCO for 10.709225316 Gbps range.\n");
            printf("Setting AMCC S19520 for SONET_RATE_SEL (refclk*64).\n");
        }
        break;
    case THREEP_MODE_10P3:
        /* THREEP_MODE_10P3 is a more generalized version of THREEP_MODE_10GBE.
        * It operates at the same VCO frequency, but uses a refclk*64 instead
        * refclk*66 to achieve the VCO frequency.
        */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, 0,
            0, EDT_AMCC_S19250_GBE_RATE_SEL);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, EDT_AMCC_S19250_SONET_RATESEL,
            0, EDT_AMCC_S19250_SONET_RATESEL);
        /* Set up for 10.3125 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_RX_VCO_RNG_10GBER, 0, EDT_AMCC_S19250_RX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_94,
            EDT_AMCC_S19250_RX_VCO_RES_10GBER, 0, EDT_AMCC_S19250_RX_VCO_RES_MASK);
        /* PAEQ_LINKOPT1 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1C,
            EDT_AMCC_S19250_PAEQ_LINKOPT1_10GBER , 0, EDT_AMCC_S19250_PAEQ_LINKOPT1_MASK);
        /* PAEQ_LINKOPT2 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1E,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_10GBER, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_MASK);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1F,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_10GBER, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_MASK);
        if (verbose)
        {
            printf("Setting AMCC S19520 RX for 10.3125 Gbps range.\n");
            printf("Setting AMCC S19520 for SONET_RATE_SEL (refclk*64).\n");
        }
        break;
    case THREEP_MODE_OTU2E:
    case THREEP_MODE_OTU2F:
    case OTU1E_RATE:
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, 0,
            0, EDT_AMCC_S19250_GBE_RATE_SEL);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_05, EDT_AMCC_S19250_SONET_RATESEL,
            0, EDT_AMCC_S19250_SONET_RATESEL);
        /* Set up for 11.0957 or 11.3176 Gbps */
        /* VCO RANGE */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_81,
            EDT_AMCC_S19250_RX_VCO_RNG_11P3, 0, EDT_AMCC_S19250_RX_VCO_RNG_MASK);
        /* VCO RESISTOR PROCESS */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_94,
            EDT_AMCC_S19250_RX_VCO_RES_11P3, 0, EDT_AMCC_S19250_RX_VCO_RES_MASK);
        /* PAEQ_LINKOPT1 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1C,
            EDT_AMCC_S19250_PAEQ_LINKOPT1_11P3 , 0, EDT_AMCC_S19250_PAEQ_LINKOPT1_MASK);
        /* PAEQ_LINKOPT2 */
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1E,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_11P3, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_UPPER_MASK);
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_1F,
            EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_11P3, 0, EDT_AMCC_S19250_PAEQ_LINKOPT2_LOWER_MASK);
        if (verbose)
        {
            printf("Setting AMCC S19520 RX for 11.0957 Gbps range.\n");
            printf("Setting AMCC S19520 for SONET_RATE_SEL (refclk*64).\n");
        }
        break;
    default:
        edt_perror("edt_threep_amcc_config_rx: invalid mode");
    }

    /* reset the receive section */
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_04, 0, 0, EDT_AMCC_S19250_RX_RSTB);
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_04, EDT_AMCC_S19250_RX_RSTB,
        0, EDT_AMCC_S19250_RX_RSTB);
}

/*
* the AMCC has to be unreset before you can talk to it via the serial port
* this routine will check if it is unreset and if not enable it and
* set up the rx and tx for THREEP default operation
*
*/


void
edt_threep_amcc_chk_enable( EdtDev * edt_p, int mode)
{
    unsigned char byte;
    /* read the enable register */
    byte = edt_reg_read( edt_p, THREEP_P0_ENABLE);

    if ((byte & LIU_EN) == 0)
    {
        edt_reg_write( edt_p, THREEP_P0_ENABLE, byte | LIU_EN );

        /* init rx and tx after enable use SDH as default */
        edt_threep_amcc_config_rx( edt_p, mode);
        edt_threep_amcc_config_tx( edt_p, mode);
    }
}

int 
edt_threep_amcc_clk_mode(double freq)

{

    if (freq > 9000000000.0)
        freq /= 1000000000.0;

    if (freq < 9.7)
        return -1;
    else if (freq < 10.1)
        return THREEP_MODE_SDH;
    else if (freq < 10.4)
        return THREEP_MODE_10P3;
    else if (freq < 10.9)
        return THREEP_MODE_G709;
    else if (freq <= 11.4)
        return THREEP_MODE_OTU2E;
    else
        return -1;
}

/*
* set local loopback
*/
void
edt_threep_amcc_local_loop( EdtDev * edt_p, int set)
{
    if (set)
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_01, 0, 0, EDT_AMCC_S19250_NOT_DLEB);
    else
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_01, EDT_AMCC_S19250_NOT_DLEB,
        0, EDT_AMCC_S19250_NOT_DLEB);
}

/*
* set remote loopback
*/
void
edt_threep_amcc_remote_loop( EdtDev * edt_p, int set)
{
    if (set)
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, 0, 0, EDT_AMCC_S19250_NOT_LLEB);
    else
        edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_02, EDT_AMCC_S19250_NOT_LLEB,
        0, EDT_AMCC_S19250_NOT_LLEB);
}

/*
* set  transmit prbs test
* code is a byte to select the prbs code
*/
void
edt_threep_amcc_set_tx_prbs( EdtDev * edt_p, int code)
{
    unsigned char byte;
    /* set the code gen/chk */
    edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_89, code, 0, EDT_AMCC_S19250_PRBS_MASK);
    /* enable tx tester */
    byte = edt_threep_amcc_reg_set_bits( edt_p, EDT_AMCC_S19250_ADDR_86, EDT_AMCC_S19250_TX_BIST_EN,
        0, EDT_AMCC_S19250_TX_BIST_EN);
}

/* si5326 settings to initialize the si5326 to run 155.52 from the SI 570 unmodified */
#if 0
static
Edt2WireRegArray threep_15552[EDT_SI5326_NREGS+1] = {
    {  0,0x14},
    {  1,0xe4},
    {  2,0xa2},
    {  3,0x5},
    {  4,0x92},
    {  5,0xed},
    {  6,0x2d},
    {  7,0x2a},
    {  8,0x0},
    {  9,0xc0},
    { 10,0x8},
    { 11,0x48},
    { 16,0x0},
    { 17,0x80},
    { 18,0x0},
    { 19,0x29},
    { 20,0x3e},
    { 21,0xff},
    { 22,0xdf},
    { 23,0x1f},
    { 24,0x3f},
    { 25,0x80},
    { 31,0x0},
    { 32,0x0},
    { 33,0x3},
    { 34,0x0},
    { 35,0x0},
    { 36,0x3},
    { 40,0x80},
    { 41,0x1},
    { 42,0x37},
    { 43,0x0},
    { 44,0x0},
    { 45,0x4d},
    { 46,0x0},
    { 47,0x0},
    { 48,0x4d},
    { 55,0x0},
    {131,0x1f},
    {132,0x2},
    {136,0x40},
    {142,0x0},
    {143,0x0},
    {256,0}
};
#endif

int
edt_threep_si5326_load_array(EdtDev *edt_p,  Edt2WireRegArray *vec, int device)
{
    int mapindex;
    int r;
    for (mapindex = 0; vec[mapindex].offset < 256 && mapindex < EDT_SI5326_NREGS ; mapindex++)
    {
        if (!vec[mapindex].read_only)
        {
            edt_serial_dev_reg_write(edt_p, THREEP_I2C_DEVICE, device, vec[mapindex].offset, vec[mapindex].value);
            r = edt_serial_dev_reg_read(edt_p, THREEP_I2C_DEVICE, device, vec[mapindex].offset);
#if 0
            if (r != vec[mapindex].value)
                printf("Unable to write at offset %d value %02x != %02x\n",
                vec[mapindex].offset, vec[mapindex].value, r);
#endif


        }
    }
    return 0;
}

int
edt_threep_si5326_dump(EdtDev *edt_p, int device)
{

    int mapindex;

    for (mapindex = 0; si5326regs_map[mapindex].name != NULL ; mapindex++)
    {
        u_int v = edt_get_two_wire_value(edt_p, 
            si5326regs_map + mapindex,
            THREEP_I2C_DEVICE, 
            device);


        printf("%-20s: %02x\n", si5326regs_map[mapindex].name, v);


    }

    return 0;
}

int
edt_threep_configure_clock(EdtDev *edt_p, double frequency, int port, 
                            EdtSI570 * clock_values)

{
    int verbose = edt_msg_get_level(edt_msg_default_handle()) &
        EDTLIB_MSG_INFO_1;

    double clk_value;
    u_int  dev_address;

    switch(port)
    {
    case 0:
        dev_address = THREEP_P0_REF_CLK;
        clk_value   = THREEP_P0_CLOCK_VALUE;
        break;

    case 1:
        dev_address = THREEP_P1_REF_CLK;
        clk_value   = THREEP_P1_CLOCK_VALUE;
        break;

    case 2:
        dev_address = THREEP_P2_REF_CLK;
        clk_value   = THREEP_P2_CLOCK_VALUE;
        break;

    }

    
    if (verbose > 3)
    {
        printf("ch0: ref clock\n");
        edt_si570_dump(edt_p, THREEP_I2C_DEVICE, dev_address);
    }

    edt_si570_reset(edt_p,THREEP_I2C_DEVICE, dev_address);

    edt_si570_read_values(edt_p, THREEP_I2C_DEVICE, dev_address,
       clock_values);

    if (verbose > 2)
        edt_si570_print(clock_values, clk_value);

    edt_vco_si570_compute(clk_value,
        frequency, 
        clock_values);

    edt_si570_write_values(edt_p, THREEP_I2C_DEVICE, dev_address,
        clock_values);

    if (port == 0)
    {
        edt_msleep(50);
        edt_threep_si5326_load_array(edt_p, threep_15552, THREEP_DEV_XMT_CLK);
        if (verbose > 3)
            edt_threep_si5326_dump(edt_p, THREEP_DEV_XMT_CLK);
        edt_msleep(20);
    }

    return 0;
}

int
edt_threep_configure_clks(EdtDev *edt_p, EdtThreePClocks *clocks)

{

    edt_threep_configure_clock(edt_p, clocks->ch0_clock_freq, 0, 
        &clocks->ch0_clock_values);
    edt_threep_configure_clock(edt_p, clocks->ch1_clock_freq, 1, 
        &clocks->ch1_clock_values);
    edt_threep_configure_clock(edt_p, clocks->ch2_clock_freq, 2, 
        &clocks->ch2_clock_values);

    return 0;
}

void
dump_threep_freq_cntrs( EdtDev * edt_p, int en)
{
    int  mrd = 0;
    int sleep = 50;

    edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x00); //disable/clear all freq cntrs
    edt_msleep(100);
    if (en & 0x01)
    {
        //channel 0 RX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x00 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch0 rx
        edt_msleep(sleep);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch0: rx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd/.0099998/1000000);
        //channel 0 TX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x30 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch0 tx
        edt_msleep(10);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch0: tx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd/.0099998/1000000);
    }
    if (en & 0x02)
    {
        //channel 1 RX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x10 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch1 rx
        edt_msleep(sleep);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch1: rx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd*2/.0099998/1000000);
        //channel 1 TX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x40 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch1 tx
        edt_msleep(10);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch1: tx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd*2/.0099998/1000000);
    }
    if (en & 0x04)
    {
        //channel 2 RX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x20 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch2 rx
        edt_msleep(sleep);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch2: rx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd*2/.0099998/1000000);
        //channel 1 TX
        mrd = 0;
        edt_reg_write(edt_p, THREEP_FREQ_CNT_EN, 0x50 | (THREEP_FREQ_CNT_EN_MSK | en)); //enable all freq cntrs, select ch2 tx
        edt_msleep(10);
        mrd = edt_reg_read(edt_p, THREEP_FREQ_CNT);
        printf("ch2: tx: 0x%06x = %d;\tfreq=%f Mhz\n", mrd, mrd, mrd*2/.0099998/1000000);
    }
}

#define EXT_ADDRESS     0
#define BUSY_STAT       0
#define SERIAL_XFER_BSY_MSK     0x80
#define SERIAL_NACK_MSK 0x40
#define READ_ADD_DATA   1
#define WRITE_ADD       2
#define WRITE_DATA      3
#define READ_ADD_DATA2  4

uint_t
edt_3p_mn_ser_dev_reg_write(EdtDev * edt_p, 
                            uint_t base_desc,
                            uint_t device_id,
                            uint_t address, 
                            uint_t value)
{
    /* check for transfer busy */
    /*  if( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_NACK_MSK) != 0)
    {
    printf("!!!!write NACK!!!!\n");
    return 1;
    }*/
    while ( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_XFER_BSY_MSK) != 0)
        edt_msleep(0);
    edt_reg_write(edt_p, base_desc+EXT_ADDRESS, device_id);
    edt_reg_write(edt_p, base_desc+WRITE_ADD, address & 0xff);
    edt_reg_write(edt_p, base_desc+WRITE_DATA, value);
    while ( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_XFER_BSY_MSK) != 0)
        edt_msleep(0);
    if( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_NACK_MSK) != 0)
    {
        printf("!!!!write NACK1!!!\n");
        return 1;
    }
    return 0;
}

uint_t
edt_3p_mn_ser_dev_reg_read(EdtDev * edt_p, 
                           uint_t base_desc, 
                           uint_t device_id,
                           uint_t address,
                           uint_t* bytes)
{
    uint_t read_val = 0;
    uint_t upbyte = 0;
    uint_t lowbyte = 0;
    /* check for transfer busy *//*
                                 if( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_NACK_MSK) != 0)
                                 {
                                 printf("----read NACK0---\n");
                                 return(1);
                                 }*/
    while ( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_XFER_BSY_MSK) != 0)
        edt_msleep(0);
    edt_reg_write(edt_p, base_desc+EXT_ADDRESS, device_id);
    edt_reg_write(edt_p, base_desc+READ_ADD_DATA, address & 0xff);

    /* wait for transfer complete */
    if( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_NACK_MSK) != 0)
    {
        printf("----read NACK1---\n");
        return(1);
    }
    while ( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_XFER_BSY_MSK) != 0)
        edt_msleep(0);
    upbyte = edt_reg_read(edt_p, base_desc+READ_ADD_DATA2);
    lowbyte = edt_reg_read(edt_p, base_desc+READ_ADD_DATA);

    *bytes = (upbyte<<8) | lowbyte;
    while ( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_XFER_BSY_MSK) != 0)
        edt_msleep(0);
    if( ((edt_reg_read(edt_p, base_desc+BUSY_STAT)) & SERIAL_NACK_MSK) != 0)
    {
        printf("----read NACK2---\n");
        return(1);
    }
    return(0);
}

uint_t
edt_3p_adt7461_reg_read(EdtDev * edt_p, 
                        uint_t base_desc, 
                        uint_t device_id,
                        uint_t address,
                        uint_t* bytes)
{
    int retval = 0;
    retval = edt_3p_mn_ser_dev_reg_write(edt_p, base_desc, device_id, address, address /*value*/);
    if(retval)
        return retval;
    //edt_msleep(100);
    retval = edt_3p_mn_ser_dev_reg_read(edt_p, base_desc, device_id, address, bytes);
    *bytes = (*bytes>>8);
    //edt_msleep(100);
    return retval;

}

uint_t
edt_3p_adt7461_reg_write(EdtDev * edt_p, 
                         uint_t base_desc, 
                         uint_t device_id,
                         uint_t address,
                         uint_t value)
{
    int retval = 0;
    retval = edt_3p_mn_ser_dev_reg_write(edt_p, base_desc, device_id, address, value);
    //printf("3p_adt wr reval=%d\n",retval);
    return retval;
}

double
edt_3p_v6_temp(EdtDev * edt_p)

{
    int retry;
    int status;
    double ext_temp;

    uint_t byte;


    retry = 5;
    do{
        retry--;
        status = edt_3p_adt7461_reg_read(edt_p, THREEP_ADT7461_BASE, 3, 0x01, &byte);
    }while(status && retry != 0);

    
    if(status)
        exit(1);
    edt_msleep(100);
    ext_temp = (double)byte;

    retry = 5;
    do{
        retry--;
        status = edt_3p_adt7461_reg_read(edt_p, THREEP_ADT7461_BASE, 3, 0x10, &byte);
    }while(status && retry != 0);

    if(status)
        exit(1);

    ext_temp = ext_temp + .25*(double)(byte>>6);
    
    return ext_temp;
}

---