edt_pll Struct Reference

Structure to set up phase locked loop parameters. More...

#include <libedt.h>

Data Fields
int	m
int	n
int	v
int	r
int	h
int	l
int	x

Detailed Description

Structure to set up phase locked loop parameters.

Some of these values go into the AV9110-02 PLL chip and others set up pre-scalars in the FPGA.

Field Documentation

m

int edt_pll::m

AV9110 reference frequency divide range 3-127.

n

int edt_pll::n

AV9110 VCO feedback frequency divide range 3-127.

v

int edt_pll::v

AV9110 VCO feedback frequency pre-scalar range 1 or 8.

r

int edt_pll::r

AV9110 VCO output divider 1, 2, 4, 8.

h

int edt_pll::h

Xilinx high speed divider (VCO output) 1, 3, 5, 7.

l

int edt_pll::l

Xilinx divide by n 1-64.

x

int edt_pll::x

Xilinx AV9110 pre-scale of 30 MHz oscillator 1-256.

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The documentation for this struct was generated from the following file:

• libedt.h (git e5e16a8, 2025-04-29)