clsim_lib.c File Reference

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Detailed Description

Camera Link Simulator Library, for use with PCI DV CLS and PCIe DV C-Link with Simulator FPGA loaded.

Definition in file clsim_lib.c.

#include "edtinc.h"
#include "clsim_lib.h"
#include "edt_si570.h"

Go to the source code of this file.

Functions
int	pdv_cls_dep_sanity_check (PdvDev *pdv_p)
	Checks for inconsistencies in the configuration (stub).
void	pdv_cls_dump_geometry (PdvDev *pdv_p)
	Prints board geometry only to stdout.
void	pdv_cls_dump_state (PdvDev *pdv_p)
	Prints the board state to stdout.
double	pdv_cls_frame_time (PdvDev *pdv_p)
	Computes and returns the frame time in milliseconds.
int	pdv_cls_get_hgap (PdvDev *pdv_p)
	Computes the horizontal gap value based on the difference between active clocks (hblank) and the total clocks.
int	pdv_cls_get_vgap (PdvDev *pdv_p)
	Computes the vertical gap value based on the difference between active lines(vblank) and the total lines.
void	pdv_cls_init_serial (PdvDev *pdv_p)
	Re-intializes and enables the serial communication.
void	pdv_cls_set_cfg_bit (PdvDev *pdv_p, int reg, int mask, int state)
	General bit setting routine, primarily for internal use by other library routines.
void	pdv_cls_set_clock (PdvDev *pdv_p, double freq)
	Set the clock frequency (MHz).
void	pdv_cls_set_datacnt (PdvDev *pdv_p, int state)
	Enables / disables internal image data generation.
int	pdv_cls_set_dep (PdvDev *pdv_p)
	Initializes simulator values based on PdvDependent structure in pdv_p.
void	pdv_cls_set_depth (PdvDev *pdv_p, int value)
void	pdv_cls_set_dvalid (PdvDev *pdv_p, u_char skip, u_char mode)
	Set the values for Data Valid (DVAL), timing.
void	pdv_cls_set_fill (PdvDev *pdv_p, u_char left, u_char right)
	Sets the left and right fill values when READVAL is set.
void	pdv_cls_set_firstfc (PdvDev *pdv_p, int state)
	Enables / disables frame count in the first word of each frame.
void	pdv_cls_set_height (PdvDev *pdv_p, int height, int vblank)
	Set the height of outgoing frames, as well as the number of lines (vgap) between lines.
void	pdv_cls_set_intlven (PdvDev *pdv_p, int state)
	Enables or disables four-tap interleaving.
void	pdv_cls_set_led (PdvDev *pdv_p, int state)
	Controls state of the board's green LED.
void	pdv_cls_set_line_timing (PdvDev *pdv_p, int width, int taps, int Hfvstart, int Hfvend, int Hlvstart, int Hlvend, int Hrvstart, int Hrvend)
	Set the values for frame valid (FVAL), line valid (LVAL), and read valid (RVAL) timing.
void	pdv_cls_set_linescan (PdvDev *pdv_p, int state)
	When set, once the start-of-frame conditions are met, the simulator runs forever, emulating a linescan camera (as if the total vertical active and total vertical count maximum were set to infinity.
void	pdv_cls_set_lvcont (PdvDev *pdv_p, int state)
	Enables / disables line valid timing during vertical blanking.
void	pdv_cls_set_readvalid (PdvDev *pdv_p, u_short HrvStart, u_short HrvEnd)
	Sets the horizontal start and end positions of the ReadValid signal.
void	pdv_cls_set_rven (PdvDev *pdv_p, int state)
	Enables or disables ReadValid Enable (RVEN).
void	pdv_cls_set_size (PdvDev *pdv_p, int taps, int depth, int width, int height, int hblank, int totalwidth, int vblank, int totalheight)
	Set the width and height of the simulator frame.
void	pdv_cls_set_smallok (PdvDev *pdv_p, int state)
	Sets simulator FIFO for small (less than 16KB) images.
void	pdv_cls_set_trigframe (PdvDev *pdv_p, int state)
	Set to enable frame-valid triggering.
void	pdv_cls_set_trigline (PdvDev *pdv_p, int state)
	Set to enable line-valid triggering.
void	pdv_cls_set_trigpol (PdvDev *pdv_p, int polarity)
	Sets the trigger polariry.
void	pdv_cls_set_trigsrc (PdvDev *pdv_p, int select)
	Selects which input pins to look at for external trigger.
void	pdv_cls_set_uartloop (PdvDev *pdv_p, int state)
	Enables or disables UART looping (echo) of serial data.
void	pdv_cls_set_width (PdvDev *pdv_p, int width, int hblank)
	Set the width of outgoing lines, as well as the number of clocks (hgap) between lines.
void	pdv_cls_set_width_lval_rval (PdvDev *pdv_p, int width, int hblank, int hlvstart, int hlvend, int hrvstart, int hrvend)
	Set the width of outgoing lines, as well as the number of clocks (hgap) between lines and start and end of line valid and read valid.
void	pdv_cls_setup_interleave (PdvDev *pdv_p, short tap0start, short tap0delta, short tap1start, short tap1delta, short tap2start, short tap2delta, short tap3start, short tap3delta)
	Sets the start address and delta for each tap.
void	pdv_cls_sim_start (PdvDev *pdv_p)
	Clears the CFG register including the FIFO_RESET bit (bit 3, 0x08) which clears the fifo and starts the simulator.
void	pdv_cls_sim_stop (PdvDev *pdv_p)
	Sets the CFG register FIFO_RESET bit (bit 3, 0x08) which stops the simulator.
void	pe8dvcls_set_clock (PdvDev *pdv_p, double target)
	Set si570 clock speed in microseconds.

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Function Documentation

void pdv_cls_set_cfg_bit	(	PdvDev *	pdv_p,
		int	reg,
		int	mask,
		int	state
	)

General bit setting routine, primarily for internal use by other library routines.

Parameters:

	pdv_p	pointer to pdv device structure returned by pdv_open
	reg	the register to set (see PDV_CLSIM* registers in edtreg.h)
	mask	mask for specific bits to set, leaving others unchanged
	state	state to set specific bit(s)

Returns:

void

Definition at line 224 of file clsim_lib.c.

void pdv_cls_set_dvalid	(	PdvDev *	pdv_p,
		u_char	skip,
		u_char	mode
	)

Set the values for Data Valid (DVAL), timing.

Parameters:

	pdv_p	pointer to pdv device structure returned by pdv_open
	skip	how many clocks to skip (ALERT CHECK THIS)
	mode	mode on or off (ALERT CHECK THIS)

Returns:

void

Definition at line 862 of file clsim_lib.c.

void pe8dvcls_set_clock	(	PdvDev *	pdv_p,
		double	target
	)

Set si570 clock speed in microseconds.

Not to be called directly -- use pdv_cls_set_clock()

Parameters:

	pdv_p	pointer to pdv device structure returned by pdv_open
	target	clock speed in microseconds (ALERT CHECK THIS)

Returns:

void

Definition at line 826 of file clsim_lib.c.

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