00001
00002
00033 #include "edtinc.h"
00034 #include "edt_ocx.h"
00035 #include "lib_sdh.h"
00036 #include "initpcd.h"
00037
00062 edt_sdh_t *
00063 edt_sdh_board_setup(int unitNo, int configure_board)
00064 {
00065 EdtDev *edt_p;
00066 edt_sdh_t *sdh_p;
00067 char *rate_str;
00068 int tmp;
00069
00070
00071
00072
00073
00074
00075 if (configure_board != ATTACH_TO_CURRENT)
00076 {
00077 char *cwd = (char *) calloc(1, PATH_MAX);
00078 char *configFile;
00079
00080 if (cwd)
00081 {
00082 if (getcwd(cwd, PATH_MAX) == NULL)
00083 {
00084 edt_perror((char *)"getcwd");
00085 free(cwd);
00086 return NULL;
00087 }
00088 }
00089 else
00090 {
00091 edt_perror((char *) "calloc");
00092 return NULL;
00093 }
00094 if (chdir("/opt/EDTpcd"))
00095 {
00096 if (chdir("c:\\edt\\pcd"))
00097 {
00098 free(cwd);
00099 edt_perror((char *) "cdir /opt/EDTpcd and chdir c:\\edt\\pcd failed");
00100 return NULL;
00101 }
00102 }
00103
00104 switch (configure_board)
00105 {
00106 case STM1_RATE:
00107 configFile = "pcd_config/stm1_frm.cfg";
00108 rate_str = "STM1_RATE";
00109 break;
00110 case STM4_RATE:
00111 configFile = "pcd_config/stm4_frm.cfg";
00112 rate_str = "STM4_RATE";
00113 break;
00114 case STM16_RATE:
00115 configFile = "pcd_config/stm16_frm.cfg";
00116 rate_str = "STM16_RATE";
00117 break;
00118 case STM64_RATE:
00119 configFile = "pcd_config/stm64_frm.cfg";
00120 rate_str = "STM64_RATE";
00121 break;
00122 default:
00123 edt_msg(EDT_MSG_FATAL, "edt_sdh_board_setup() illegal second argument:\n\tMust be one of ATTACH_TO_CURRENT, STM1_RATE, STM4_RATE, or STM16_RATE\n");
00124 tmp = chdir(cwd);
00125 free(cwd);
00126 return NULL;
00127 }
00128
00129
00130
00131
00132
00133
00134 {
00135 char cmd[128];
00136 sprintf(cmd, "./initpcd -u %d -f %s", unitNo, configFile);
00137 if (edt_system(cmd))
00138 {
00139 edt_perror(configFile);
00140 tmp = chdir(cwd);
00141 free(cwd);
00142 return NULL;
00143 }
00144 }
00145
00146
00147 tmp = chdir(cwd);
00148 }
00149 else
00150 {
00151 rate_str = "ATTACH_TO_CURRENT";
00152 }
00153
00154 if ((edt_p = edt_open((char *)"pcd", unitNo)) == NULL)
00155 {
00156 edt_perror((char *)"edt_open");
00157 return NULL;
00158 }
00159
00160
00161
00162
00163 if ((sdh_p = (edt_sdh_t *) calloc(1, sizeof(edt_sdh_t))) == NULL)
00164 {
00165 edt_perror((char *) "calloc");
00166 return NULL;
00167 }
00168
00169 sdh_p->edt_p = edt_p;
00170
00171
00172 sdh_p->unitNo = unitNo;
00173 sdh_p->e1buf_version = edt_intfc_read(edt_p, 0x7C) >> 4;
00174 printf("e1 buffer structure version 0x%x\n", sdh_p->e1buf_version);
00175 sdh_p->m_numRingBufs = 8;
00176 sdh_p->m_ringBufSize = 32 * 1024 *
00177 ((sdh_p->e1buf_version == 0) ? sizeof(edt_sdh_e1_buf_t) : sizeof(edt_sdh_e1_buf_v2_t));
00178
00179
00180
00181 if (configure_board)
00182 {
00183 edt_disable_channels(sdh_p->edt_p, 0xffffffff);
00184 edt_flush_fifo(sdh_p->edt_p);
00185 }
00186
00187 return sdh_p;
00188 }
00189
00190
00202 int
00203 edt_sdh_release_board(edt_sdh_t *sdh_p)
00204 {
00205 if (sdh_p == NULL)
00206 return -1;
00207
00208 if (sdh_p->edt_p != NULL)
00209 {
00210 edt_close(sdh_p->edt_p);
00211 }
00212
00213 free(sdh_p);
00214
00215 return 0;
00216 }
00217
00230 int
00231 edt_sdh_set_ring_buffer_size_number(edt_sdh_t *sdh_p, int bufsize, int numbufs)
00232 {
00233 if (sdh_p == NULL)
00234 return -1;
00235
00236 sdh_p->m_ringBufSize = bufsize;
00237 sdh_p->m_numRingBufs = numbufs;
00238
00239 return 0;
00240 }
00241
00242
00254 int
00255 edt_sdh_channel_disable(edt_sdh_t *sdh_p, int channel)
00256 {
00257 if ((sdh_p != NULL) && (sdh_p->edt_p != NULL))
00258 {
00259 edt_disable_channel(sdh_p->edt_p, channel);
00260 return 0;
00261 }
00262 else
00263 return -1;
00264 }
00265
00277 int
00278 edt_sdh_channel_enable(edt_sdh_t *sdh_p, int channel)
00279 {
00280 if ((sdh_p != NULL) && (sdh_p->edt_p != NULL))
00281 {
00282 edt_enable_channel(sdh_p->edt_p, channel);
00283 return 0;
00284 }
00285 else
00286 return -1;
00287 }
00288
00300 int
00301 edt_sdh_board_set_clock_to_system_time(edt_sdh_t *sdh_p)
00302 {
00303 if ((sdh_p != NULL) && (sdh_p->edt_p != NULL))
00304 {
00305
00306 EdtDev *edt_p = sdh_p->edt_p;
00307
00308 int test_cal = 0;
00309 int test_zero = 0;
00310 int setup = 0;
00311 int set_time = 1;
00312 int showtimes = 0;
00313 int auto_adjust = 0;
00314 int adjust_value = 0;
00315 int auto_measure = 0;
00316 int set_adjust = 0;
00317 int disable_adj = 0;
00318 int enable_adj = 0;
00319 int auto_secs = 5;
00320 int interval = 1000;
00321 int launch_checker = 0;
00322 int set_time_error = 0;
00323 int time_error = 1;
00324 double stable_adj = 0;
00325 EdtTimeController controller;
00326 u_int base = EDT_SSTM_COUNTS & 0xff0000;
00327
00328 memset(&controller,0,sizeof(controller));
00329 controller.adjustment_scalar = 2;
00330 controller.adjust_sample = 60;
00331 controller.max_error = 200;
00332 controller.tolerance = 20;
00333 controller.loops = 1;
00334 controller.check_interval = 600;
00335 controller.active = 1;
00336
00337 if (edt_p->devid == PE8LX16_ID ||
00338 edt_p->devid == PE8LX32_ID ||
00339 edt_p->devid == PE8G2V7_ID ||
00340 edt_p->devid == PE4AMC16_ID)
00341 base = 0x10ff0000;
00342
00343 edt_init_time_controller(&controller, edt_p, base);
00344
00345 edt_sstm_set_to_sys(&controller);
00346
00347 return 0;
00348 }
00349 else
00350 {
00351 return -1;
00352 }
00353 }
00354
00383 int
00384 edt_sdh_start_stm1_to_e1_channel(edt_sdh_t *sdh_p, int stm1, int channel, int callbackControl, int ( *e1_callback ) ( void * e1buf, void *auxArg ), void *callbackArg, int loops)
00385 {
00386
00387 edt_sdh_start_stm1_to_e1_channel_timeout(sdh_p, stm1, channel, callbackControl, e1_callback, callbackArg, loops, NULL, 0, 0);
00388 }
00389
00421 int
00422 edt_sdh_start_stm1_to_e1_channel_timeout(edt_sdh_t *sdh_p, int stm1, int channel, int callbackControl, int ( *e1_callback ) ( void * e1buf, void *auxArg ), void *callbackArg, int loops, int ( *timeout_callback ) ( edt_sdh_t * sdh_p, int channel), int timeout, int timeout_ok)
00423 {
00424 int loop, i, done = 0;
00425
00426 u_char *e1buf;
00427 int buffers_running;
00428 int e1buf_size = (sdh_p->e1buf_version == 0) ? sizeof(edt_sdh_e1_buf_t) : sizeof(edt_sdh_e1_buf_v2_t);
00429 int e1s_per_ringBuffer = (sdh_p->m_ringBufSize / e1buf_size);
00430
00431
00432 static int bufferOffset = 0, init = 1;
00433
00434 printf("sdh %p stm1 %x chan %d\n", sdh_p, stm1, channel);
00435
00436 printf("unit %d chan %d stm1 %d numRingBufs %d ringBufSize %d\n", sdh_p->unitNo, channel, stm1, sdh_p->m_numRingBufs, sdh_p->m_ringBufSize);
00437 if ((sdh_p->stm1[channel].edt_p = edt_open_channel((char *)"pcd", sdh_p->unitNo, channel)) == NULL)
00438 {
00439 edt_perror((char *)"edt_open_channel");
00440 return -1;
00441 }
00442
00443
00444 edt_indirect_reg_write(sdh_p->stm1[channel].edt_p, (0x000086 | (channel << 12)), stm1);
00445 printf("stm1 map to dma channel reg %06x: %02x\n\n", (0x000086 | (channel << 12)),
00446 edt_indirect_reg_read(sdh_p->stm1[channel].edt_p, (0x000086 | (channel << 12))));
00447
00448 edt_set_timeout_ok(sdh_p->stm1[channel].edt_p, timeout_ok);
00449 edt_set_rtimeout(sdh_p->stm1[channel].edt_p, timeout);
00450
00451 sdh_p->current_stm1 = stm1;
00452 sdh_p->current_channel = channel;
00453 edt_sdh_channel_disable(sdh_p, channel);
00454 edt_msleep(100);
00455
00456 edt_configure_ring_buffers(sdh_p->stm1[channel].edt_p, sdh_p->m_ringBufSize, sdh_p->m_numRingBufs, EDT_READ, NULL);
00457 edt_flush_channel(sdh_p->stm1[channel].edt_p, channel) ;
00458 edt_start_buffers(sdh_p->stm1[channel].edt_p, sdh_p->m_numRingBufs);
00459 buffers_running = sdh_p->m_numRingBufs;
00460 edt_flush_channel(sdh_p->stm1[channel].edt_p, channel) ;
00461
00462 printf("loops %d\n", loops);
00463
00464
00465
00466 sdh_p->stm1[channel].active = 1;
00467 edt_sdh_channel_enable(sdh_p, channel);
00468
00469
00470 for (loop = 0; !done && (sdh_p->stm1[channel].active) && (loops == 0 || loop < loops); ++loop)
00471 {
00472 if (e1buf = edt_wait_for_buffers(sdh_p->stm1[channel].edt_p, 1))
00473 {
00474 int status;
00475 if (timeout_callback != NULL)
00476 status = edt_get_wait_status(sdh_p->stm1[channel].edt_p);
00477 else
00478 status = EDT_WAIT_OK;
00479
00480
00481 switch (status)
00482 {
00483 case EDT_WAIT_TIMEOUT:
00484 case EDT_WAIT_OK_TIMEOUT:
00485 {
00486 done = timeout_callback(sdh_p, channel);
00487 }
00488 break;
00489
00490
00491 case EDT_WAIT_OK:
00492 {
00493 -- buffers_running;
00494
00495 if (callbackControl == CALLBACK_PER_E1_FRAME)
00496 {
00497 for (i = 0; i < e1s_per_ringBuffer; ++i)
00498 {
00499
00500
00501 (void) (*e1_callback)(e1buf + (e1buf_size * i), callbackArg);
00502 }
00503 }
00504 else if (callbackControl == CALLBACK_PER_RING_BUFFER)
00505 {
00506 (void) (*e1_callback)(e1buf, callbackArg);
00507 }
00508
00509 edt_start_buffers(sdh_p->stm1[channel].edt_p, 1);
00510 ++ buffers_running;
00511
00512 }
00513 break;
00514
00515
00516 }
00517 }
00518 }
00519
00520 while (buffers_running > 0)
00521 {
00522 (void) edt_wait_for_buffers(sdh_p->stm1[channel].edt_p, 1);
00523 -- buffers_running;
00524 }
00525
00526 edt_msleep(100);
00527
00528 edt_disable_ring_buffers(sdh_p->stm1[channel].edt_p);
00529
00530 return 0;
00531 }
00532
00544 int
00545 edt_sdh_stop_stm1_to_e1_channel(edt_sdh_t *sdh_p, int stm1)
00546 {
00547
00548 if (sdh_p == NULL || stm1 < 0 || stm1 > 15)
00549 return -1;
00550
00551 sdh_p->stm1[stm1].active = 0;
00552
00553 return 0;
00554 }
00555
00556 u_char
00557 edt_indirect_reg_read(EdtDev *edt_p, u_int addr)
00558 {
00559 return edt_reg_read(edt_p, INDREG_1BYTE | (addr & 0xffffff));
00560 }
00561
00562 void
00563 edt_indirect_reg_write(EdtDev *edt_p, u_int addr, u_char val)
00564 {
00565 edt_reg_write(edt_p, INDREG_1BYTE | (addr & 0xffffff), val);
00566 }
00567
00568
00579 int
00580 edt_sdh_loss_of_light(edt_sdh_t *sdh_p)
00581 {
00582 int chanStatusReg = 0x22;
00583 int lol = edt_intfc_read(sdh_p->edt_p, chanStatusReg);
00584
00585 return (lol & 0x10);
00586 }
00587 int
00588 edt_sdh_loss_of_light_input_0(edt_sdh_t *sdh_p)
00589 {
00590 int chanStatusReg = 0x22;
00591 int lol = edt_intfc_read(sdh_p->edt_p, chanStatusReg);
00592
00593 return (lol & 0x10);
00594 }
00595 int
00596 edt_sdh_loss_of_light_input_1(edt_sdh_t *sdh_p)
00597 {
00598 int chanStatusReg = 0x32;
00599 int lol = edt_intfc_read(sdh_p->edt_p, chanStatusReg);
00600
00601 return (lol & 0x10);
00602 }
00603
00604
00615 int
00616 edt_sdh_stm_is_framed(edt_sdh_t *sdh_p)
00617 {
00618 int chanReceiveStatusReg = 0x94;
00619 int framed = edt_intfc_read(sdh_p->edt_p, chanReceiveStatusReg);
00620
00621 return (framed & 0x01);
00622 }
00623 int
00624 edt_sdh_stm_is_framed_input_0(edt_sdh_t *sdh_p)
00625 {
00626 int chanReceiveStatusReg = 0x94;
00627 int framed = edt_intfc_read(sdh_p->edt_p, chanReceiveStatusReg);
00628
00629 return (framed & 0x01);
00630 }
00631 int
00632 edt_sdh_stm_is_framed_input_1(edt_sdh_t *sdh_p)
00633 {
00634 int chanReceiveStatusReg = 0xD4;
00635 int framed = edt_intfc_read(sdh_p->edt_p, chanReceiveStatusReg);
00636
00637 return (framed & 0x01);
00638 }
00639
00640
00653 int
00654 edt_sdh_reg_read_stm1_status(edt_sdh_t *sdh_p, u_char *result)
00655 {
00656 u_char stm1;
00657
00658 if (sdh_p == NULL || result == NULL)
00659 return -1;
00660
00661 for (stm1 = 0; stm1 < 16; ++stm1)
00662 result[stm1] = edt_indirect_reg_read(sdh_p->edt_p, 0x000080 | (stm1 << 12));
00663
00664 return 0;
00665 }
00666
00679 u_char
00680 edt_sdh_reg_read_vc4vc3_b3_error_count(edt_sdh_t *sdh_p, int channel, u_short *result)
00681 {
00682 int vc4vc3;
00683 int au43pl;
00684
00685 memset(result, 0, sizeof(u_short) * 3);
00686
00687
00688 au43pl = edt_indirect_reg_read(sdh_p->edt_p, 0x000108 | (channel << 12));
00689
00690 for (vc4vc3 = 0; vc4vc3 < 3; ++vc4vc3)
00691 {
00692 result[vc4vc3] = edt_indirect_reg_read(sdh_p->edt_p, 0x000182 | (channel << 12) | (vc4vc3 << 3));
00693 result[vc4vc3] |= (edt_indirect_reg_read(sdh_p->edt_p, 0x000183 | (channel << 12) | (vc4vc3 << 3)) << 8);
00694
00695 if (au43pl == 0xff)
00696 break;
00697 }
00698
00699 return au43pl;
00700 }
00701
00713 u_char
00714 edt_sdh_reg_read_vc4vc3_MF_indicator(edt_sdh_t *sdh_p, int channel, u_char *result)
00715 {
00716 int vc4vc3;
00717 int au43pl;
00718
00719 memset(result, 0, sizeof(u_char) * 3);
00720
00721
00722 au43pl = edt_indirect_reg_read(sdh_p->edt_p, 0x000108 | (channel << 12));
00723
00724 for (vc4vc3 = 0; vc4vc3 < 3; ++vc4vc3)
00725 {
00726 result[vc4vc3] = edt_indirect_reg_read(sdh_p->edt_p, 0x000185 | (channel << 12) | (vc4vc3 << 3));
00727
00728 if (au43pl == 0xff)
00729 break;
00730 }
00731
00732 return au43pl;
00733 }
00734
00747 int
00748 edt_sdh_reg_read_E4_frame_status(edt_sdh_t *sdh_p, u_char *result)
00749 {
00750 u_char channel;
00751
00752 if (sdh_p == NULL || result == NULL)
00753 return -1;
00754
00755 memset(result, 0, sizeof(u_char) * 16);
00756
00757 for (channel = 0; channel < 16; ++channel)
00758 result[channel] = edt_indirect_reg_read(sdh_p->edt_p, 0x000200 | (channel << 12));
00759
00760 return 0;
00761 }
00762
00775 int
00776 edt_sdh_reg_set_E4_frame_disable(edt_sdh_t *sdh_p, int channel, int disable)
00777 {
00778 int arg = (disable) ? 1 : 0;
00779
00780 if (sdh_p == NULL || channel < 0 || channel > 15)
00781 return -1;
00782
00783 edt_indirect_reg_write(sdh_p->edt_p, 0x000210 | (channel << 12), arg);
00784
00785 return 0;
00786 }
00787
00800 int
00801 edt_sdh_reg_read_E3_frame_status(edt_sdh_t *sdh_p, int channel, u_char *result)
00802 {
00803 int e3;
00804
00805 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
00806 return -1;
00807
00808 memset(result, 0, sizeof(u_char) * 4);
00809
00810 for (e3 = 0; e3 < 4; ++e3)
00811 result[e3] = edt_indirect_reg_read(sdh_p->edt_p, 0x000280 | (channel << 12) | (e3 << 5));
00812
00813 return 0;
00814 }
00815
00828 int
00829 edt_sdh_reg_read_E2_frame_status(edt_sdh_t *sdh_p, int channel, u_char *result)
00830 {
00831 int e3, e2;
00832
00833 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
00834 return -1;
00835
00836 memset(result, 0, sizeof(u_char) * 16);
00837
00838 for (e3 = 0; e3 < 4; ++e3)
00839 {
00840 for (e2 = 0; e2 < 4; ++e2)
00841 {
00842 result[(e3 << 2) | e2] = edt_indirect_reg_read(sdh_p->edt_p, 0x000300 | (channel << 12) | (e3 << 5) | (e2 << 2));
00843 }
00844 }
00845
00846 return 0;
00847 }
00848
00861 u_char
00862 edt_sdh_reg_read_E1_frame_status(edt_sdh_t *sdh_p, int channel, u_char *result)
00863 {
00864 int e3, e2, e1;
00865 int tug3, tug2, vc12;
00866 u_char e3_frame_stat;
00867
00868 memset(result, 0, sizeof(u_char) * 64);
00869
00870
00871 e3_frame_stat = edt_indirect_reg_read(sdh_p->edt_p, 0x000280 | (channel << 12));
00872
00873 if (e3_frame_stat & 1)
00874 {
00875
00876
00877 for (e3 = 0; e3 < 4; ++e3)
00878 {
00879 for (e2 = 0; e2 < 4; ++e2)
00880 {
00881 for (e1 = 0; e1 < 4; ++e1)
00882 {
00883 int e321 = (e3 << 5) | (e2 << 2) | e1;
00884 int e321_index = (e3 * 16) + (e2 * 4) + e1;
00885
00886 result[e321_index] =
00887 edt_indirect_reg_read(sdh_p->edt_p, 0x000380 | (channel << 12) | e321);
00888 }
00889 }
00890 }
00891 }
00892 else
00893 {
00894
00895
00896 for (tug3 = 0; tug3 < 3; ++tug3)
00897 {
00898 for (tug2 = 0; tug2 < 7; ++tug2)
00899 {
00900 for (vc12 = 0; vc12 < 3; ++vc12)
00901 {
00902 int tug3_2vc12 = (tug3 << 5) | (tug2 << 2) | vc12;
00903 int tug3_2vc12_index = (tug3 * 21) + (tug2 * 3) + vc12;
00904
00905 result[tug3_2vc12_index] =
00906 edt_indirect_reg_read(sdh_p->edt_p, 0x000380 | (channel << 12) | tug3_2vc12);
00907 }
00908 }
00909 }
00910 }
00911
00912 return e3_frame_stat;
00913 }
00914
00927 int
00928 edt_sdh_reg_set_E1_frame_disable(edt_sdh_t *sdh_p, int channel, int disable)
00929 {
00930 int arg = (disable) ? 1 : 0;
00931 int i;
00932
00933 if (sdh_p == NULL || channel < 0 || channel > 15)
00934 return -1;
00935
00936 for (i = 0; i < 128; ++i)
00937 edt_indirect_reg_write(sdh_p->edt_p, 0x000400 | (channel << 12) | i, arg);
00938
00939 return 0;
00940 }
00941
00942
00955 int
00956 edt_sdh_reg_read_vc3_b3_error_count(edt_sdh_t *sdh_p, int channel, u_short *result)
00957 {
00958 int vc3;
00959
00960 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
00961 return -1;
00962
00963 memset(result, 0, sizeof(u_short) * 3);
00964
00965 for (vc3 = 0; vc3 < 3; ++vc3)
00966 {
00967 result[vc3] = edt_indirect_reg_read(sdh_p->edt_p, 0x000582 | (channel << 12) | (vc3 << 3));
00968 result[vc3] |= (edt_indirect_reg_read(sdh_p->edt_p, 0x000583 | (channel << 12) | (vc3 << 3)) << 8);
00969 }
00970
00971 return 0;
00972 }
00973
00986 int
00987 edt_sdh_reg_read_vc3_signal_label(edt_sdh_t *sdh_p, int channel, u_char *result)
00988 {
00989 int vc3;
00990
00991 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
00992 return -1;
00993
00994 memset(result, 0, sizeof(u_char) * 3);
00995
00996 for (vc3 = 0; vc3 < 3; ++vc3)
00997 {
00998 result[vc3] = edt_indirect_reg_read(sdh_p->edt_p, 0x000584 | (channel << 12) | (vc3 << 3));
00999 }
01000
01001 return 0;
01002 }
01003
01015 u_char
01016 edt_sdh_reg_read_vc4vc3_path_overhead(edt_sdh_t *sdh_p, int channel, u_char *result)
01017 {
01018 int vc4vc3, poh;
01019 int au43pl;
01020
01021 memset(result, 0, sizeof(u_char) * 27);
01022
01023
01024 au43pl = edt_indirect_reg_read(sdh_p->edt_p, 0x000108 | (channel << 12));
01025
01026 for (vc4vc3 = 0; vc4vc3 < 3; ++vc4vc3)
01027 {
01028 for (poh = 0; poh < 9; ++poh)
01029 {
01030 result[(vc4vc3*9) + poh] = edt_indirect_reg_read(sdh_p->edt_p, 0x000800 | (channel << 12) | (vc4vc3 << 4) | poh);
01031
01032 if (au43pl == 0xff)
01033 break;
01034 }
01035 }
01036
01037 return au43pl;
01038 }
01039
01051 int
01052 edt_sdh_reg_read_tu3vc3_path_overhead(edt_sdh_t *sdh_p, int channel, u_char *result)
01053 {
01054 int vc3, poh;
01055
01056 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
01057 return -1;
01058
01059 memset(result, 0, sizeof(u_char) * 27);
01060
01061 for (vc3 = 0; vc3 < 3; ++vc3)
01062 {
01063 for (poh = 0; poh < 9; ++poh)
01064 {
01065 result[(vc3*9) + poh] = edt_indirect_reg_read(sdh_p->edt_p, 0x000880 | (channel << 12) | (vc3 << 4) | poh);
01066 }
01067 }
01068
01069 return 0;
01070 }
01071
01083 int
01084 edt_sdh_reg_read_vc12_path_overhead(edt_sdh_t *sdh_p, int channel, u_char *result)
01085 {
01086 int tug3vc3, tug2, vc12, poh;
01087
01088 if (sdh_p == NULL || result == NULL || channel < 0 || channel > 15)
01089 return -1;
01090
01091 memset(result, 0, sizeof(u_char) * 252);
01092
01093 for (tug3vc3 = 0; tug3vc3 < 3; ++tug3vc3)
01094 {
01095 for (tug2 = 0; tug2 < 7; ++tug2)
01096 {
01097 for (vc12 = 0; vc12 < 3; ++vc12)
01098 {
01099 for (poh = 0; poh < 4; ++poh)
01100 {
01101 result[(tug3vc3*84) + (tug2*12) + (vc12*3) + poh] =
01102 edt_indirect_reg_read(sdh_p->edt_p, 0x000A00 | (channel << 12) | (tug3vc3 << 7) | (tug2 << 4) | (vc12 << 2) | poh);
01103 }
01104 }
01105 }
01106 }
01107
01108 return 0;
01109 }
01110
01111
01112 u_int
01113 edt_sdh_e1_buf_time_secs(edt_sdh_t *sdh_p, void *e1buf_p)
01114 {
01115 if (sdh_p->e1buf_version == 0)
01116 {
01117 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01118 return p->e1_status.time_secs;
01119
01120 }
01121 else if (sdh_p->e1buf_version == 1)
01122 {
01123 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01124 return p->e1_status.time_secs;
01125 }
01126 else
01127 return -1;
01128 }
01129
01130 u_int
01131 edt_sdh_e1_buf_time_fsecs(edt_sdh_t *sdh_p, void *e1buf_p)
01132 {
01133 if (sdh_p->e1buf_version == 0)
01134 {
01135 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01136 return p->e1_status.time_fsecs;
01137
01138 }
01139 else if (sdh_p->e1buf_version == 1)
01140 {
01141 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01142 return p->e1_status.time_fsecs;
01143 }
01144 else
01145 return -1;
01146 }
01147
01148 u_int
01149 edt_sdh_e1_buf_e1_number(edt_sdh_t *sdh_p, void *e1buf_p)
01150 {
01151 if (sdh_p->e1buf_version == 0)
01152 {
01153 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01154 return p->e1_status.e1_number;
01155
01156 }
01157 else if (sdh_p->e1buf_version == 1)
01158 {
01159 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01160 return p->e1_status.e1_number;
01161 }
01162 else
01163 return -1;
01164 }
01165
01166 u_int
01167 edt_sdh_e1_buf_odd_frame(edt_sdh_t *sdh_p, void *e1buf_p)
01168 {
01169 if (sdh_p->e1buf_version == 0)
01170 {
01171 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01172 return p->e1_status.odd_frame;
01173
01174 }
01175 else if (sdh_p->e1buf_version == 1)
01176 {
01177 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01178 return p->e1_status.odd_frame;
01179 }
01180 else
01181 return -1;
01182 }
01183
01184 u_int
01185 edt_sdh_e1_buf_frame_lock(edt_sdh_t *sdh_p, void *e1buf_p)
01186 {
01187 if (sdh_p->e1buf_version == 0)
01188 {
01189 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01190 return p->e1_status.frame_lock;
01191
01192 }
01193 else if (sdh_p->e1buf_version == 1)
01194 {
01195 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01196 return p->e1_status.frame_lock;
01197 }
01198 else
01199 return -1;
01200 }
01201
01202 u_int
01203 edt_sdh_e1_buf_length(edt_sdh_t *sdh_p, void *e1buf_p)
01204 {
01205 if (sdh_p->e1buf_version == 0)
01206 {
01207 return -1;
01208 }
01209 else if (sdh_p->e1buf_version == 1)
01210 {
01211 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01212 return p->e1_status.length;
01213 }
01214 else
01215 return -1;
01216 }
01217
01218 u_int
01219 edt_sdh_e1_buf_e1_tag(edt_sdh_t *sdh_p, void *e1buf_p)
01220 {
01221 if (sdh_p->e1buf_version == 0)
01222 {
01223 return -1;
01224 }
01225 else if (sdh_p->e1buf_version == 1)
01226 {
01227 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01228 return p->e1_status.e1_tag;
01229 }
01230 else
01231 return -1;
01232 }
01233
01234 u_int
01235 edt_sdh_e1_buf_vc12_buf(edt_sdh_t *sdh_p, void *e1buf_p)
01236 {
01237 if (sdh_p->e1buf_version == 0)
01238 {
01239 return -1;
01240
01241 }
01242 else if (sdh_p->e1buf_version == 1)
01243 {
01244 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01245 return p->e1_status.vc12_buf;
01246 }
01247 else
01248 return -1;
01249 }
01250
01251 u_char *
01252 edt_sdh_e1_buf(edt_sdh_t *sdh_p, void *e1buf_p)
01253 {
01254 if (sdh_p->e1buf_version == 0)
01255 {
01256 edt_sdh_e1_buf_t *p = (edt_sdh_e1_buf_t *) e1buf_p;
01257 return p->e1_buf;
01258
01259 }
01260 else if (sdh_p->e1buf_version == 1)
01261 {
01262 edt_sdh_e1_buf_v2_t *p = (edt_sdh_e1_buf_v2_t *) e1buf_p;
01263 return p->e1_buf;
01264 }
01265 else
01266 return NULL;
01267 }