lib_ocm.c

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/* #pragma ident "@(#)lib_ocm.c 1.43 10/26/09 EDT" */

#include "edtinc.h"

#include "edt_bitload.h"

#include "edt_ocm.h"
#include "edt_ocx.h"
#include "edt_oc192.h"


/**********************************
* These functions work the same 
* on both OCM and OC192
**********************************/

void
edt_ocx_enable_framing_errors(EdtDev *edt_p, int state)

{

    u_int mezzanine_offset = 0;

    if (edt_p->channel_no & 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset,
        OCM_EN_ERROR_COUNT, state);

}


int 
edt_ocx_get_framing_errors(EdtDev *edt_p, EdtOCXFrameErrors *err_p)

{
    u_int mezzanine_offset = 0;

    if (edt_p->channel_no & 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }
    /* Assume frame counts are enabled */

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset , 
        OCM_ERROR_COUNT_HOLD, 1);

    err_p->b1_errors = edt_reg_read(edt_p, 
        OCM_CH0_B1_ERROR_CNT + mezzanine_offset);
    err_p->b1_error_mask = (u_char) edt_reg_read(edt_p, 
        OCM_CH0_B1_ERROR_MASK + mezzanine_offset);
    err_p->b2_errors = edt_reg_read(edt_p, 
        OCM_CH0_B2_ERROR_CNT + mezzanine_offset);
    err_p->m1_errors = edt_reg_read(edt_p, 
        OCM_CH0_M1_ERROR_CNT + mezzanine_offset);
    err_p->lof_errors = edt_reg_read(edt_p, 
        OCM_CH0_LOF_CNT + mezzanine_offset);
    err_p->frame_pattern_errors = edt_reg_read(edt_p, 
        OCM_CH0_FRM_PAT_CNT + mezzanine_offset);
    err_p->false_frame_errors = edt_reg_read(edt_p, 
        OCM_CH0_FALSE_FRM_CNT + mezzanine_offset);

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset , 
        OCM_ERROR_COUNT_HOLD, 0);

    return 0;
}


int
edt_ocx_lock_local_clock(EdtDev *edt_p, int timeout)

{

    FENTER("edt_ocx_lock_clocks");

    if (edt_wait_register_bits_high(edt_p, PCD_STAT, LOCAL_SYS_LOCK,timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rBaseboard System clock not locked");
        return -1;
    }

    edt_msg(EDTLIB_MSG_INFO_1,"Local System clocks locked \n");

    return 0;

}

int
edt_ocx_lock_channel_clock(EdtDev *edt_p, int channel, int timeout)

{
    int base_offset;

    FENTER("edt_ocx_lock_clocks");

    base_offset = (channel & 1) ? OFFSET_CH1_BASE:0;

    if (edt_wait_register_bits_high (edt_p, OCM_CH0_ENABLE + base_offset,
        SYS_LOCK,timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rMezzanine System clock not locked");
        return -1;

    }

    return 0;

}

int
edt_msdv_load_default_mezzanine(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc = 0;

    char *bitname = "dvb_asi.bit";

    if (cfg->mezz_0)
        if (cfg->mezz_0[0])
            bitname = cfg->mezz_0;

    rc = edt_bitload(edt_p, NULL, bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    return rc;
}

int
edt_net10g_load_default_mezzanine(EdtDev *edt_p,EdtOCConfig *cfg)

{
    int rc = 0;

    char *bitname = "net10g_5v_sdh.bit";

    FENTER("edt_net10g_load_default_mezzanine");
    if (cfg->mezz_0)
        if (cfg->mezz_0[0])
            bitname = cfg->mezz_0;

    rc = edt_bitload(edt_p, NULL, bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    if (rc == 0)
    {
        bitname = "net10g_s3_cfg.bit";

        if (cfg->mezz_1)
            if (cfg->mezz_1[0])
                bitname = cfg->mezz_1;

        rc = edt_bitload(edt_p, NULL, bitname, BITLOAD_FLAGS_MEZZANINE | BITLOAD_FLAGS_CH1, 0);
    }

    return rc;
}

/***************************************
*
* OCM specific functions
* Most have equivalent OC192 functions
*
**************************************/

int
edt_ocm_lock_clocks(EdtDev *edt_p, int timeout)

{

    if (edt_ocx_lock_local_clock(edt_p, timeout) ||
        edt_ocx_lock_channel_clock(edt_p, 0, timeout) ||
        edt_ocx_lock_channel_clock(edt_p, 1, timeout))

        return -1;

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}


const char *
edt_ocm_mezz_filename(EdtDev *edt_p, EdtOCConfig *cfg)

{

    char *target_bitfile;

    switch (cfg->line_rate) {
        case OC3_RATE:      
        case OC12_RATE:     
        case STM1_RATE:
        case STM4_RATE:
            target_bitfile="ocm12.bit";
            break;

        case STM16_RATE:            
        case OC48_RATE:     
            target_bitfile="ocm48.bit";
            break;

        case GIGE_RATE:
            target_bitfile="ethernet.bit";
            break;

        default:
            target_bitfile = NULL;

    }

    return target_bitfile;
}

int
edt_ocm_load_default_mezzanine(EdtDev *edt_p, EdtOCConfig *cfg)

{

    int rc = 0;
    int flags  = BITLOAD_FLAGS_OVR | BITLOAD_FLAGS_OCM;
    int rate = OC48_RATE;

    const char *bitname;

    if (edt_p->channel_no == 0)
        rate = (cfg->line_rate)?cfg->line_rate:OC48_RATE;

    if (cfg->mezz_0 && cfg->mezz_0[0])
        bitname = cfg->mezz_0;
    else
        bitname = edt_ocm_mezz_filename(edt_p, cfg);

    rc = edt_bitload(edt_p, NULL, bitname, flags, 0);

    if (rc == 0)
    {
        flags |= BITLOAD_FLAGS_CH1;

        if (cfg->mezz_1 && cfg->mezz_1[0])
            bitname = cfg->mezz_1;
        else
            bitname = edt_ocm_mezz_filename(edt_p, cfg);

        rc = edt_bitload(edt_p, NULL, bitname, flags, 0);

    }

    return rc;

}

int
edt_ocm_speed_capable(int channel, EdtLineRate line_rate)

{
    int rc = -1;
    switch (line_rate) {
        case STM1_RATE:
        case STM4_RATE:
        case OC3_RATE:      
        case OC12_RATE:     
        case GIGE_RATE:
        case STM16_RATE:            
        case OC48_RATE:     
        case OTU1_RATE:
            rc = 0;
            break;

        case GIG10E_RATE:
        case OTU2_RATE:
        case STM64_RATE:
        case OC192_RATE:
            rc =  -1;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Unknown bit rate %d\n", line_rate);
            rc =  -1;

    } 
    return rc;
}



int
edt_ocm_has_mezz_bitfile(EdtDev *edt_p, const char *bitfile_name)

{
    int channel = edt_p->channel_no & 1;
    char *ch_id;
    int rc;

    FENTER_S("edt_ocm_has_correct_bitfile",bitfile_name);

    if (channel == 0)
    {
        ch_id  = edt_p->bfd.mezz_name0;
    }
    else
    {
        ch_id  = edt_p->bfd.mezz_name1;
    }

    /* check correct bitfile for channel 0 */
    rc = strcmp(ch_id, bitfile_name);

    FRETURN_I("edt_ocm_has_correct_bitfile",rc);

    return rc;

}
int
edt_ocm_set_clock_select(EdtDev *edt_p, EdtLineRate line_rate)

{
    int channel = edt_p->channel_no & 1;
    int clk_select = CLK_SONET_SDH;
    int clk_val = OC3_STM1;
    int base_offset = 0;
    int mezzanine_offset = 0;
    int read_byte;


    FENTER_I("edt_ocm_set_clock_select", line_rate);

    switch (line_rate)
    {
    case OC3_RATE:          
    case STM1_RATE:
        clk_val = OC3_STM1;
        break;

    case OC12_RATE:      
    case STM4_RATE:
        clk_val = OC12_STM4;
        break;

    case STM16_RATE:        
    case OC48_RATE:         
        clk_val = OC48_STM16;
        break;

    case GIGE_RATE:
        clk_val = OC24;
        clk_select = CLK_GE | 0x4;
        break;

    case OTU1_RATE:
        /* set LIU for OC48, clk src to 166.62857 */
        clk_val = OC48_STM16;
        clk_select = CLK_FEC;
        break;
    }

    if (channel == 1) 
    {
        base_offset = OFFSET_CH1_BASE;
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    /* select the oscillator frequency */
    read_byte = edt_reg_read(edt_p, OCM_TX_CONFIG + mezzanine_offset); 
    read_byte &= ~CLOCK_SEL_MSK;
    read_byte |= clk_select;
    edt_reg_write(edt_p, OCM_TX_CONFIG + mezzanine_offset, read_byte );
    /* set LIU to correct multiplier */
    read_byte = edt_reg_read(edt_p, OCM_CH0_CONFIG0 + base_offset);  
    read_byte &= ~RX_SEL_MSK;
    read_byte |= clk_val;
    edt_reg_write(edt_p, OCM_CH0_CONFIG0 + base_offset , read_byte);  


    FRETURN("edt_ocm_set_clock_select");

    return 0;

}

int
edt_ocm_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int done = 0;
    /* it takes 200 ms every time through */
    int t;
    int timeout = cfg->timeout;
    int timer = 0;
    int timed_out = 0;

    uint_t base_offset = 0;
    int channel = edt_p->channel_no & 1;

    if (channel == 1)
    {
        base_offset = OFFSET_CH1_BASE;
    }

    /* Reset front end DPLLs */
    edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset,  ~(SLK_EN | PLL_EN));

    edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, SYS_EN);

    if (cfg->flags & EDT_OCX_ENABLE_MEM && (edt_p->channel_no == 0))
        edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, RAM_EN );
    else
        edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~RAM_EN );

    if (cfg->flags & EDT_OCX_PRBS_EN)
    {
        edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, PLL_EN);
        return 0;
    }

    if (edt_p->channel_no < 2 && !(cfg->flags & EDT_OCX_NO_SIG_DET))
    {
        if (!edt_ocx_channel_signal_detect(edt_p, timeout))
        {
            edt_msg(EDT_MSG_WARNING,"\rChannel %d no signal detected -  check signal input", channel);
            return -1;
        }  

    }
    timer = 0;
    timed_out = 0;

    while (done == 0 && !timed_out)
    {
        /* enable SLK */
        edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, SLK_EN); 
        
        /* test if SLK is locked */
        /* LOL is a reliable indication of some lock problems but not all */
        t = edt_wait_register_bits_low_timer(edt_p, OCM_CH0_STATUS+base_offset, LOL,  cfg->receive_dcm_timeout);
        
        if (t <  (int) cfg->receive_dcm_timeout)
        {
            
            edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, PLL_EN); 
        
            t = edt_wait_register_bits_high_timer(edt_p, OCM_CH0_ENABLE + base_offset, RX_LOCK, cfg->receive_dcm_timeout);

            timer = t;

            if (t >=  (int) cfg->receive_dcm_timeout)
            {
                edt_msg(EDT_MSG_WARNING,"\rChannel %d FPGA PLL not locked check signal input type", channel);
                /* reset slk and dcm enable */
                edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
                timed_out = TRUE;
            }
            else
                done = TRUE;
        }
        else
        {
            edt_msg(EDT_MSG_WARNING,"\rChannel %d LIU PLL not locked check signal input type", channel);
            /* reset slk and dcm enable */
            edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
        }

        if (timeout)
            timed_out = timer >= (int) cfg->receive_dcm_timeout;

    }

    if (timed_out)
    {
        edt_msg(EDT_MSG_FATAL,"\rChannel %d unable to lock PLL -  check signal input", channel);
        return -1;
    }
    else
        edt_msg(EDT_MSG_INFO_1,"\rChannel %d PLL locked                    \n", channel);

    return 0;

}

int
edt_ocm_check_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int done = 0;
    /* it takes 200 ms every time through */
    int t;
    int timeout = cfg->timeout;
    int timer = 0;
    int timed_out = 0;

    uint_t base_offset = 0;
    int channel = edt_p->channel_no & 1;

    if (channel == 1)
    {
        base_offset = OFFSET_CH1_BASE;
    }

    /* Reset front end DPLLs */
    edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset,  ~(SLK_EN | PLL_EN));

    edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, SYS_EN);

    if (edt_p->channel_no < 2 )
    {
        if (!edt_ocx_channel_signal_detect(edt_p, timeout))
        {
            edt_msg(EDT_MSG_WARNING,"\rChannel %d no signal detected -  check signal input", channel);
            return 0;
        }  

    }



    while (done == 0 && !timed_out)
    {
        /* enable SLK */
        edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, SLK_EN); 
        
        /* test if SLK is locked */
        /* LOL is a reliable indication of some lock problems but not all */
        t = edt_wait_register_bits_low_timer(edt_p, OCM_CH0_STATUS+base_offset, LOL,  cfg->receive_dcm_timeout);
        
        printf("SLK_EN time = %d\n", t);
       
        printf("enable %02x\n", edt_reg_read(edt_p, OCM_CH0_ENABLE + base_offset));  

        if (t <  (int) cfg->receive_dcm_timeout)
        {
            
            edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, PLL_EN); 
        
            t = edt_wait_register_bits_high_timer(edt_p, OCM_CH0_ENABLE + base_offset, RX_LOCK, cfg->receive_dcm_timeout);

            printf("DCM time = %d\n", t);
            timer = t;

            if (t >=  (int) cfg->receive_dcm_timeout)
            {
                edt_msg(EDT_MSG_WARNING,"\rChannel %d FPGA PLL not locked check signal input type", channel);
                /* reset slk and dcm enable */
                edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
                timed_out = TRUE;
            }
            else
                done = TRUE;
        }
        else
        {
            edt_msg(EDT_MSG_WARNING,"\rChannel %d LIU PLL not locked check signal input type", channel);
            /* reset slk and dcm enable */
            edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
        }

        if (timeout)
            timed_out = timer >= (int) cfg->receive_dcm_timeout;

    }

    if (timed_out)
    {
        edt_msg(EDT_MSG_FATAL,"\rChannel %d unable to lock PLL -  check signal input", channel);
        return -1;
    }
    else
        edt_msg(EDT_MSG_INFO_1,"\rChannel %d PLL locked                    \n", channel);

    return 0;

}
int
edt_ocm_channel_setup(EdtDev *edt_p, EdtOCConfig *cfg)


{
    int channel = edt_p->channel_no;
    int base_offset = 0;
    int mezzanine_offset = 0;
    u_char rx_ctrl ;
    u_char rx_filter ;

    FENTER("edt_ocm_channel_setup");

    if (edt_p->mezz.id == MEZZ_OC192)
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0);     
    }


    if (channel == 1)
    {
        base_offset = OFFSET_CH1_BASE;
        mezzanine_offset = OFFSET_CH1_MEZ;

    }

    /* set local loopback if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, LOCAL_LOOP, (cfg->flags & EDT_OCX_LOOPBACK));

    /* set remote loopback if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, REMOTE_LOOP, (cfg->flags & EDT_OCX_REMOTE_LPBK));

    /* set LIU PRBS7 generator if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, PRBS_EN, (cfg->flags & EDT_OCX_PRBS_EN));


    rx_ctrl = (u_char) edt_reg_read(edt_p, OCM_RX_CTRL + mezzanine_offset);

    if (cfg->flags & EDT_OCX_FRAMED)
    {
        rx_ctrl |= FRAME_EN;
        if ((cfg->flags & EDT_OCX_DESCRAMBLE) == 0)
            rx_ctrl |= DISABLE_SCRAM;
        else
            rx_ctrl &= ~DISABLE_SCRAM;
    }
    else
        rx_ctrl &= ~FRAME_EN;

    if (cfg->flags & EDT_OCX_ENABLE_MEM)
        rx_ctrl |= RX_DATA_SRC_2G;
    else
        rx_ctrl &= ~RX_DATA_SRC_2G;

    edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, rx_ctrl); 

    rx_filter = (u_char) edt_reg_read(edt_p, OCM_RX_FILTER + mezzanine_offset);
    rx_filter &= ~OVERHEAD_ONLY; 
    if (cfg->flags & EDT_OCX_OVHD_ONLY) 
    {
        if (cfg->flags & EDT_OCX_FRAMED)
            rx_filter |= OVERHEAD_ONLY; 
        else
            edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
    }
    /* enable data substitution */
    rx_filter &= ~(EN_DATA_COUNTER | COUNT_FREERUN); 
    if (cfg->flags &  EDT_OCX_ENABLE_COUNT_DATA) 
        rx_filter |= EN_DATA_COUNTER;
    if (cfg->flags & EDT_OCX_FREERUN_COUNT_DATA)
        rx_filter |= COUNT_FREERUN;
    /* enable all bytes from ethernet 8b/10b decoder */
    rx_filter &= ~(EN_ALL_DECODED); 
    if (cfg->flags & EDT_OCX_ETHERNET_ALL_DECODE)
        rx_filter |= EN_ALL_DECODED;
    edt_reg_write(edt_p, OCM_RX_FILTER + mezzanine_offset, rx_filter); 

    FRETURN_I("edt_ocm_channel_setup",0);
    return 0;
}

int
edt_ocm_wait_for_frame(EdtDev *edt_p, int timeout)

{
    u_int cfg;
    int mezzanine_offset = 0;
    int t = 100;
    int rc = 0;

    FENTER("edt_ocm_wait_for_frame");

    if (edt_p->channel_no == 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    edt_msg(EDTLIB_MSG_INFO_1,"Waiting for frame CH%d", edt_p->channel_no);

    
    while (((cfg = edt_reg_read(edt_p, OCM_RX_STATUS + mezzanine_offset)) & FRAMED) == 0 &&
        t < timeout)
    {
        edt_msg(EDTLIB_MSG_INFO_1,".");
        cfg = edt_reg_read(edt_p, OCM_RX_CTRL + mezzanine_offset);
        edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, cfg | RESET_FRM);  /* set reset frame */
        edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, cfg);  /* clear it */
        edt_msleep(100);
        t += 100;
    }

    if (t < timeout)
        edt_msg(EDTLIB_MSG_INFO_1," framed\n");
    else
    {
        edt_msg(EDTLIB_MSG_FATAL," Framing timed out in %d ms\n", timeout);
        rc = -1;
    }

    FRETURN_I("edt_ocm_wait_for_frame", rc);

    return rc;

}

/***************************************
*
* OC192 board-specific functions
* Most other than the _mdio_ access functions
* have an euqivalent OCM function
*
**************************************/

/***************************************
*
* OC192 mdio functions to talk to the LIU
*
**************************************/


unsigned char 
edt_oc192_mdio_read(EdtDev *edt_p, unsigned char address)
{
    unsigned char result=0, byte;
    unsigned int val;
    int i;

    FENTER_I("edt_oc192_mdio_read",address);
    val = 0x60000000;
    val |= ((unsigned int) (address & 0x1f))<<18;
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
    result = 0;
    for (i=31; i>=0; i--) {
        if (i>17) {
            if (!((val>>i) & 0x1)) {
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK | SCLK_TRI);
            } else {
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
            }
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
        } else {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK | SCLK_TRI);
            if (i<=8 && i>=1) {
                byte = edt_intfc_read(edt_p, OC192_LIU_MDIO_BUS) & SDATA_IN;
                result |= ((byte>>4)<<(i-1));
            }
        }
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);

    FRETURN_I("edt_oc192_mdio_read",result);
    return result;
}

void
edt_oc192_mdio_write(EdtDev *edt_p, unsigned char address, unsigned char value)
{
    unsigned int val;
    int i;

    FENTER_I_I("edt_oc192_mdio_write",address, value);
    val = 0x50020000;
    val |= ((((unsigned int) (address & 0x1f))<<18) | (unsigned int) value);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
    for (i=31; i>=0; i--) {
        if (!((val>>i)&0x1)) {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK | SCLK_TRI);
        } else {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
        }
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);

    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SCLK) ;
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);
    FRETURN("edt_oc192_mdio_write");
}

void 
edt_oc192_mdio_init(EdtDev *edt_p)
{
    int i;

    FENTER("edt_oc192_mdio_init");

    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    for (i=32; i>=0; i--) {
        edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
        edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SCLK);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);
    FRETURN("edt_oc192_mdio_init");
}

void
edt_oc192_reset_liu(EdtDev *edt_p)

{
    FENTER("edt_oc192_reset_liu");
    /* Reset the AMCC S19235 */
    edt_intfc_write(edt_p, OC192_ENABLE, edt_intfc_read(edt_p, OC192_ENABLE) | AMCC_RST);
    edt_msleep(10);
    edt_intfc_write(edt_p, OC192_ENABLE, edt_intfc_read(edt_p, OC192_ENABLE) & ~AMCC_RST);
    edt_msleep(10);
    edt_oc192_mdio_init(edt_p);
    FRETURN("edt_oc192_reset_liu");
}

void
edt_oc192_mdio_set_clock(EdtDev *edt_p)

{

}

void
edt_oc192_mdio_set_swap(EdtDev *edt_p, int on)

{
    FENTER("edt_oc192_mdio_set_swap");
    edt_oc192_mdio_write(edt_p, 0x2, 
        (edt_oc192_mdio_read(edt_p, 0x2) & 0xfb) | ((on)? 0x2 : 0) );
    FRETURN("edt_oc192_mdio_set_swap");
}

void
edt_oc192_mdio_dump(EdtDev *edt_p)

{       
    uint_t i;

    for (i=1; i<=0x1f; i++)
        if (i<0x11 || i>0x1d)
            printf("%02xH       :  %02xH\n", i, edt_oc192_mdio_read(edt_p, (u_char) i));
}


void
edt_oc192_mdio_loopback(EdtDev *edt_p, int on)

{
    FENTER("edt_oc192_mdio_loopback");
    edt_oc192_mdio_write(edt_p, 0x1, edt_oc192_mdio_read(edt_p, 0x1) & 0xfd | ((on)? 0:0x2) );
    FRETURN("edt_oc192_mdio_loopback");
}

void
edt_oc192_mdio_set_prbs23(EdtDev *edt_p, int on)
{
    /*
    * Select prbs23 code
    */
    FENTER("edt_oc192_mdio_set_prbs23");
    edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xe7) | (on) ? 0x10 : 0);
    FRETURN("edt_oc192_mdio_set_prbs23");
}

void
edt_oc192_mdio_set_prbs31(EdtDev *edt_p, int on)
{
    /*
    * Select prbs23 code
    */
    FENTER("edt_oc192_mdio_set_prbs31");
    edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xe7) | (on) ? 0x11 : 0);
    FRETURN("edt_oc192_mdio_set_prbs31");
}

void
edt_oc192_mdio_standard(EdtDev *edt_p)

{
    FENTER("edt_oc192_mdio_standard");
    /*
    * Refclk is 155.52, turn on DATA_SWAP
    */
    edt_oc192_mdio_set_swap(edt_p, 1);

    /*
    * Bit 2-0
    * Phase offset between high speed recovered data and clock for improved BER
    * 000 => + 8.5 ps (default)
    * 111 => - 11.0 ps
    *
    * Bit 7-6
    * Post amplifier offset adjust
    * 
    */
    /* 
    * post amp equalization adjust
    * bit 4-2
    * 000               No equalization                         -0.8dB
    * 001               0% - 5%                                         1.4dB
    * 010               5% - 10%                                        2.4dB
    * .......
    * 111               30% - 35%                                       7.5dB
    */
    edt_oc192_mdio_write(edt_p, 0xe, (edt_oc192_mdio_read(edt_p, 0xe) & 0xfb) | 0x18 );

    FRETURN("edt_oc192_mdio_standard");
}

int
edt_oc192_set_liu(EdtDev *edt_p, int mode)

{
    int rc = 0;
    FENTER("edt_oc192_set_liu");

    edt_oc192_reset_liu(edt_p);
    edt_oc192_mdio_standard(edt_p);

    switch(mode)
    {
    case EDT_OC192_LIU_NORMAL:
        break;

    case EDT_OC192_LIU_LOOPBACK:
        edt_oc192_mdio_loopback(edt_p, 1);
        break;

    case EDT_OC192_LIU_REMOTE_LPBK:

        edt_oc192_mdio_write(edt_p, 1, 
            (edt_oc192_mdio_read(edt_p, 1) & ~3) | 2);
        edt_oc192_mdio_write(edt_p,2,
            (edt_oc192_mdio_read(edt_p, 2) & ~0x10));
        edt_oc192_mdio_write(edt_p, 0x5, 
            edt_oc192_mdio_read(edt_p, 0x5) & ~(0x48));

        break;

    case EDT_OC192_LIU_BIST_TX:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Transmit built in self test mode
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x40);
        /*
        * Turn on diagnostic loopback
        */
        edt_oc192_mdio_loopback(edt_p, 1);
        break;

    case EDT_OC192_LIU_BIST_TX_EXT:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Transmit built in self test mode
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x40);
        /*
        * Turn off diagnostic loopback
        */
        edt_oc192_mdio_loopback(edt_p, 0);
        break;

    case EDT_OC192_LIU_BIST_RX:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Receive built in self test mode
        * turn on line loopback
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x04);
        break;

    default:
        rc = -1;
    }

    FRETURN_I("edt_oc192_set_liu",rc);
    return rc;
}



int
edt_oc192_lock_clocks(EdtDev *edt_p, int timeout)

{


    if (edt_p->channel_no == 1 && edt_ocx_lock_local_clock(edt_p, timeout))
        return -1;

    if (edt_ocx_lock_channel_clock(edt_p, edt_p->channel_no, timeout))
        return -1;

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}

const char *
edt_ocx_rate_name(EdtLineRate line_rate)

{
    char *rc = "UNKNOWN";

    switch (line_rate) {
        case STM1_RATE:
            rc = "STM1";
            break;

        case STM4_RATE:
            rc = "STM4";
            break;

        case OC3_RATE:      
            rc = "OC3";
            break;

        case OC12_RATE:     
            rc = "OC12";
            break;

        case GIGE_RATE:
            rc = "GIGE";
            break;

        case STM16_RATE:            
            rc = "STM16";
            break;

        case OC48_RATE:     
            rc = "OC48";
            break;

        case OTU1_RATE:
            rc = "OTU1";
            break;

        case GIG10E_RATE:
            rc = "GIG10E";
            break;

        case OTU2_RATE:
            rc = "OTU2";
            break;

        case STM64_RATE:
            rc = "STM64";
            break;

        case OC192_RATE:
            rc =  "OC192";
            break;
        case OTU2E_RATE:
            rc = "OTU2E";
            break;
        case OTU2F_RATE:
            rc = "OTU2E";
            break;

        default:
            break;
    } 
    return rc;
}

int
edt_ocx_is_demuxable(EdtLineRate line_rate)

{
    u_char rc = 0;

    switch (line_rate) {
        case STM1_RATE:
         case STM4_RATE:
         case OC3_RATE:     
        case OC12_RATE:     
        case STM16_RATE:            
        case OC48_RATE:     
        case OTU1_RATE:
        case OTU2_RATE:
        case STM64_RATE:
        case OC192_RATE:
        case OTU2E_RATE:
        case OTU2F_RATE:
            return TRUE;

        default:
            break;
    } 
    return rc;
}

int edt_oc192_check_rate(EdtDev *edt_p, EdtOCConfig *cfg, EdtLineRate rate)

{
    int rc = 0;
    double r1 = 0;
    double r2 = 0;
    double r3 = 0;

    cfg->line_rate = rate;

    if (rc == 0)
    {
        /* set rate */

        edt_dtime();

        /* disable selected channel */
        edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, 0);

        /* reset lsb first which means msb is first in time */
        edt_ocx_reset_sys_en(edt_p, edt_p->channel_no);

        /* If new bitfile, resynch SYS_LOCK for this channel */
        edt_ocx_lock_channel_clock(edt_p, edt_p->channel_no, cfg->timeout);

        /* select the correct clock source */
        edt_oc192_set_clock_select(edt_p, cfg->line_rate);

        r1 = edt_dtime();
        /* OK, configure channel parameters */
        if (rc == 0)
        {
            rc = edt_oc192_channel_setup(edt_p, cfg);

            r2 = edt_dtime();

            if (rc == 0)
            {
                rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, 1, 10);

                r3 = edt_dtime();
            }
        }
    }

    return rc;

}

int edt_ocm_check_rate(EdtDev *edt_p, EdtOCConfig *cfg, EdtLineRate rate)

{
    int rc = 0;
    double r1 = 0;
    double r2 = 0;
    double r3 = 0;
    int channel = edt_p->channel_no;
    int base_offset = 0;
    int mezzanine_offset = 0;

    u_int cfg_reg = OCM_CH0_CONFIG0 + (channel)?OFFSET_CH1_BASE:0;
    u_int stat_reg =  OCM_CH0_STATUS + (channel)?OFFSET_CH1_BASE:0;
    
    cfg->line_rate = rate;

    if (rc == 0)
    {
        /* set rate */

        edt_dtime();

        /* disable selected channel */
        edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, 0);

        /* reset lsb first which means msb is first in time */
        edt_ocx_reset_sys_en(edt_p, edt_p->channel_no);

        /* If new bitfile, resynch SYS_LOCK for this channel */
        edt_ocx_lock_channel_clock(edt_p, edt_p->channel_no, cfg->timeout);

        /* select the correct clock source */
        edt_ocm_set_clock_select(edt_p, cfg->line_rate);

        r1 = edt_dtime();
        /* OK, configure channel parameters */
        if (rc == 0)
        {
            edt_reg_write(edt_p, cfg_reg, 0xf);

            
            rc = edt_ocm_channel_setup(edt_p, cfg);

            r2 = edt_dtime();

            if (rc == 0)
            {
                rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, 1, 10);

                r3 = edt_dtime();
            }
        }

    }

    return rc;

}

EdtLineRate edt_oc192_get_rate(EdtDev *edt_p, EdtOCConfig *in_cfg)

{
    EdtLineRate rc = UNKNOWN_RATE;
    EdtOCConfig cfg;
    edt_ocx_cfg_init(&cfg,
        0,
        500, 
        STM64_RATE);

    if (in_cfg)
        strncpy(cfg.mezz_0,in_cfg->mezz_0,sizeof(cfg.mezz_0)-1);

    
    
    edt_ocx_base_init(edt_p, &cfg);
    if (edt_p->channel_no & 1)
    {
        
        if (edt_oc192_check_rate(edt_p, &cfg, STM64_RATE) == 0)
        rc = STM64_RATE;
    else if (edt_oc192_check_rate(edt_p, &cfg, GIG10E_RATE) == 0)
        rc = GIG10E_RATE;
    else if (edt_oc192_check_rate(edt_p, &cfg, OTU2_RATE) == 0)
        rc = OTU2_RATE;
    else if (edt_oc192_check_rate(edt_p, &cfg, OTU2E_RATE) == 0)
        rc = OTU2E_RATE;

    }
    else
    {
        if (edt_ocm_check_rate(edt_p, &cfg, STM16_RATE) == 0)
            rc = STM16_RATE;
        else if (edt_ocm_check_rate(edt_p, &cfg, STM4_RATE) == 0)
            rc = STM4_RATE;
        else if (edt_ocm_check_rate(edt_p, &cfg, STM1_RATE) == 0)
            rc = STM1_RATE;
        else if (edt_ocm_check_rate(edt_p, &cfg, GIGE_RATE) == 0)
            rc = GIGE_RATE;
        else if (edt_ocm_check_rate(edt_p, &cfg, OTU1_RATE) == 0)
            rc = OTU1_RATE;

    }
    
    return rc;
}

int
edt_msdv_lock_clocks(EdtDev *edt_p, int timeout)

{


    if (edt_ocx_lock_local_clock(edt_p, timeout) ||
        (edt_wait_register_bits_high (edt_p, OCM_CH0_ENABLE, SYS_LOCK,timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rMezzanine System clock not locked");
        return -1;

    }

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}

char *
edt_oc192_mezz_filename_gs(EdtDev *edt_p, EdtOCConfig * cfg)

{
    char *target_bitfile = NULL;

    switch (cfg->line_rate) {
        case OC3_RATE:      
        case OC12_RATE:     
        case STM1_RATE:
        case STM4_RATE:
            if (edt_p->mezz.extended_rev > 1)
                target_bitfile="oc12m2.bit";
            else
                target_bitfile="oc12m.bit";


            break;

        case STM16_RATE:            
        case OC48_RATE:     
            if (edt_p->mezz.extended_rev > 1)
                target_bitfile="oc48m2.bit";
            else
                target_bitfile="oc48m.bit";

            break;
        case GIGE_RATE:
            if (edt_p->mezz.extended_rev > 1)
                target_bitfile="ethernet_1gbe2.bit";
            else
                target_bitfile="ethernet_1gbe.bit";
            break;

        case OTU2_RATE:
        case OTU2E_RATE:
            /* Only supported in raw bits mode (no framing, etc). */
        case STM64_RATE:
        case OC192_RATE:
            if (edt_p->mezz.extended_rev > 1)
                target_bitfile="oc192am2.bit";
            else
                target_bitfile="oc192am.bit";
            break;
        case GIG10E_RATE:

            if (cfg->flags & EDT_OCX_FRAMED)
            {
                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="ethernet_10gbe2.bit";
                else
                    target_bitfile="ethernet_10gbe.bit";

            }
            else
            {
                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="oc192am2.bit";
                else
                    target_bitfile="oc192am.bit";
            }
            break;

    }

    return target_bitfile;

}

char *
edt_oc192_mezz_filename(EdtDev *edt_p, EdtOCConfig * cfg)

{
    char *target_bitfile = NULL;

    if (edt_p->devid == PGS4_ID)
        return edt_oc192_mezz_filename_gs(edt_p, cfg);

    switch (cfg->line_rate) {
        case OC3_RATE:      
        case OC12_RATE:     
        case OC48_RATE:     
        case STM1_RATE:
        case STM4_RATE:
        case STM16_RATE:
        case OTU1_RATE:

        case OTU2_RATE:
        case OTU2E_RATE:
            /* Only supported in raw bits mode (no framing, etc). */
        case STM64_RATE:
        case OC192_RATE:

            if (edt_p->mezz.extended_rev > 1)
                target_bitfile="oc192am2.bit";
            else
                target_bitfile="oc192am.bit";

            cfg->dualmode = TRUE;

            break;


        case GIGE_RATE:
            if (cfg->flags & EDT_OCX_FRAMED)
            {
                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="ethernet_1gbe2.bit";
                else
                    target_bitfile="ethernet_1gbe.bit";
                cfg->dualmode = FALSE;
            }
            else
            {

                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="oc192am2.bit";
                else
                    target_bitfile="oc192am.bit";
                cfg->dualmode = TRUE;
            }
            break;

        case GIG10E_RATE:

            if (cfg->flags & EDT_OCX_FRAMED)
            {
                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="ethernet_10gbe2.bit";
                else
                    target_bitfile="ethernet_10gbe.bit";
                cfg->dualmode = FALSE;
            }
            else
            {
                if (edt_p->mezz.extended_rev > 1)
                    target_bitfile="oc192am2.bit";
                else
                    target_bitfile="oc192am.bit";
                cfg->dualmode = TRUE;
            }
            break;

    }

    return target_bitfile;

}


char *
edt_net10g_mezz_filename(EdtDev *edt_p, EdtOCConfig *cfg)

{
    char *target_bitfile = NULL;

    target_bitfile = "net10g_v5_sdh.bit";



    return target_bitfile;

}



int
edt_oc192_load_default_mezzanine(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc = 0;

    char *bitname = edt_oc192_mezz_filename(edt_p, cfg);


    if (cfg->mezz_0)
        if (cfg->mezz_0[0])
            bitname = cfg->mezz_0;

    printf("Loading default %s\n", bitname);

    rc = edt_bitload(edt_p, NULL, bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    if (cfg->dualmode)
        edt_reg_or(edt_p, OC192_DUAL_CHANNEL_MODE, 4);

    return rc;
}


int
edt_oc192_speed_capable(int channel, EdtLineRate line_rate)

{
    int rc = -1;

    switch (line_rate) {
        case STM1_RATE:
        case STM4_RATE:
        case STM16_RATE:            
        case OC3_RATE:      
        case OC12_RATE:     
        case OC48_RATE:     
        case GIGE_RATE:
        case OTU1_RATE:
            if ((channel & 1) == 0)
                rc = 0;
            break;

        case OTU2_RATE:
        case OTU2E_RATE:
            /* Only supported in raw bits mode (no framing, etc). */
        case GIG10E_RATE:
        case STM64_RATE:
        case OC192_RATE:
            if ((channel & 1) == 1)
                rc = 0;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Unknown bit rate %d\n", line_rate);
            rc =  -1;

    } 
    return rc;

}





int
edt_oc192_has_mezz_bitfile(EdtDev *edt_p, const char *bitfile_name)

{
    int rc;
    FENTER_S("edt_oc192_has_correct_bitfile",bitfile_name);

    rc = strcmp(edt_p->bfd.mezz_name0, bitfile_name);

    FRETURN_I("edt_oc192_has_correct_bitfile",rc);

    return rc;
}

int
edt_net10g_has_mezz_bitfile(EdtDev *edt_p, const char *bitfile_name)

{
    int rc;
    FENTER_S("edt_net10g_has_correct_bitfile",bitfile_name);

    rc = strcmp(edt_p->bfd.mezz_name0, bitfile_name);

    FRETURN_I("edt_net10g_has_correct_bitfile",rc);

    return rc;
}

int
edt_oc192_set_clock_select(EdtDev *edt_p, EdtLineRate line_rate)

{
    int channel = edt_p->channel_no;
    int clk_select = 0;

    int rc = 0;

    FENTER_I("edt_oc192_set_clock_select", line_rate);

    if ((channel & 1) == 0) 
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x0);

        return edt_ocm_set_clock_select(edt_p, line_rate);

    }
    else
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);
        /* somehow affecting module not ready */
        edt_reg_write(edt_p, OC192_ENABLE, PLL_EN);

        rc = edt_wait_register_bits_high(edt_p, OC192_ENABLE, 0x40, 300);

        /* select clock in register. */
        switch (line_rate)
        {
        case OC192_RATE:
        case STM64_RATE:
            clk_select = OC192_REFCLK_OC;
            break;
        case OTU2_RATE:
            clk_select = OC192_REFCLK_OTU2;
            break;
        case OTU2E_RATE:
            clk_select = OC192_REFCLK_10GBER_FEC;
            break;

        case GIG10E_RATE:
            clk_select = OC192_REFCLK_10GBER;
            break;

        case GIGE_RATE:
        case OC3_RATE:      
        case STM1_RATE:
        case OC12_RATE:  
        case STM4_RATE:
        case STM16_RATE:            
        case OC48_RATE:
        case OTU2F_RATE:
        default:
            /*Invalid for ch1 oc192*/
            clk_select = OC192_REFCLK_OC;
            return 1;
        }

        edt_reg_write(edt_p, OC192_REF_CLOCK, clk_select);

    }

    FRETURN("edt_oc192_set_clock_select");

    return 0;

}

double edt_oc192_get_measured_frequency(EdtDev *edt_p, int clock)

{
    u_char a0;
    int reg5051;
    double value;

    a0 = edt_reg_read(edt_p, OC192_DUAL_CHANNEL_MODE);

    a0 &= ~OC192_FREQ_MASK;

    a0 |= ((clock) << OC192_FREQ_SHIFT) & OC192_FREQ_MASK;

    edt_reg_write(edt_p, OC192_DUAL_CHANNEL_MODE, a0);

    edt_msleep(10);

    reg5051 = edt_intfc_read(edt_p, 0x51) << 8;
    /* deal with wraparound */
    if ((clock == OC192_FREQ_RX1 || clock == OC192_FREQ_TX1) && reg5051 == 0)
        reg5051 = 0x1000;
    reg5051 |= edt_intfc_read(edt_p, 0x50);


    if (clock == OC192_FREQ_RX1 || clock == OC192_FREQ_TX1)
        value = (double) reg5051 * 256 * 0.01;
    else
        value = (double) reg5051 * 64 * 0.01;

    return value;

}

void edt_oc192_set_merged_mezz(EdtDev *edt_p, int state)

{
    if (state)
    {
        edt_reg_or(edt_p, OC192_DUAL_CHANNEL_MODE, 4);
    }
    else
    {
        int val = edt_reg_read(edt_p, OC192_DUAL_CHANNEL_MODE);

        edt_reg_write(edt_p, OC192_DUAL_CHANNEL_MODE, val);
    }
}



int
edt_oc192_clear_demux(EdtDev *edt_p)

{
    int i;

    FENTER("edt_oc192_clear_demux");

    /* make sure demux is turned off */
    edt_reg_write(edt_p, OC192_DEMUX_BITMASK, 0);
    for (i=0x80;i<0x8c;i++)
        edt_reg_write(edt_p, OC192_DEMUX_MASK_ADDR, i);


    FRETURN("edt_oc192_clear_demux");

    return 0;

}

void
edt_oc192_set_framer(EdtDev *edt_p, int flags)

{

    int rx_ctrl;

    FENTER_I("edt_oc192_set_framer", flags);

    rx_ctrl = 0;
    if (flags & EDT_OCX_FRAMED)
    {
        rx_ctrl |= OC192_FRAME_EN;
        if ((flags & EDT_OCX_DESCRAMBLE) == 0)
            rx_ctrl |= OC192_DISABLE_SCRAM;
    }

    edt_reg_write(edt_p, OC192_FRAMING, rx_ctrl);

    FRETURN("edt_oc192_set_framer");

}

int
edt_oc192_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc;
    int rx_filter;
    int liu_check;

    /* AMCC received clock not locked */

    if ((edt_p->channel_no & 1) == 0)
        return edt_ocm_channel_lock_frontend(edt_p, cfg);

    if (edt_p->channel_no == 3)
        liu_check = 2;
    else
        liu_check = 1;

    if (cfg->flags & EDT_OCX_PRBS_EN)
    {
        // no need on loopback prbs
    }
    else
    {
        if ((rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, liu_check, cfg->timeout)))
        {
            edt_msg(EDTLIB_MSG_FATAL,"AMCC receiver won't lock\n");
            return -1;
        }
        else
            edt_msg(EDTLIB_MSG_INFO_1,"AMCC receiver PLL is locked\n");

        /* added 2/13/2008 jsc */

        rx_filter = 0;

        if (cfg->flags & EDT_OCX_OVHD_ONLY) 
        {
            if (cfg->flags & EDT_OCX_FRAMED)
                rx_filter |= OVERHEAD_ONLY; 
            else
                edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
        }
        if (cfg->flags & EDT_OCX_ODU_KEEP_OVHD)
        {
            if (cfg->flags & EDT_OCX_FRAMED)
                rx_filter |= ODU_MASKED_PLUS_OVHD;
            else
                edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");

        }
        if (cfg->flags & EDT_OCX_ODU_NO_FEC)
        {
            if (cfg->flags & EDT_OCX_FRAMED)
                rx_filter |= ODU_NO_FEC;
            else
                edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");

        }
        if (cfg->flags & EDT_OCX_ODU_PASS_THRU)
        {
            if (cfg->flags & EDT_OCX_FRAMED)
                rx_filter |= ODU_PASS_THRU;
            else
                edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");

        }
        edt_reg_write(edt_p, OC192_RCV_FILTER, rx_filter); 

    }

    edt_reg_write(edt_p, OC192_ENABLE, 0);
    edt_reg_write(edt_p, OC192_ENABLE, 0x4);
    edt_reg_write(edt_p, OC192_ENABLE, 0xc);
    edt_reg_write(edt_p, OC192_ENABLE, 0x1c);
    edt_msleep(100);
    edt_reg_write(edt_p, OC192_ENABLE, 0x1e);
    edt_msleep(50);

    if (edt_p->channel_no == 1)
    {
        /* Received DCM not locked */
        if ((rc = edt_wait_register_bits_high(edt_p, OC192_ENABLE, 0xf0, cfg->receive_dcm_timeout)))
        {
            edt_msg(EDTLIB_MSG_FATAL,"Receive DCM won't lock\n");
            return -1;

        }
        else
            edt_msg(EDTLIB_MSG_INFO_1,"Receive DCM Locked\n");

    }


    return 0;

}

int
edt_net10g_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc;
    int rx_filter;

    /* AMCC received clock not locked */

    if ((rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, 0x1, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"AMCC receiver won't lock\n");
        return -1;
    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"AMCC receiver PLL is locked\n");

    /* added 2/13/2008 jsc */

    rx_filter = (u_char) edt_reg_read(edt_p, OC192_RCV_FILTER);
    rx_filter &= ~OVERHEAD_ONLY; 
    if (cfg->flags & EDT_OCX_OVHD_ONLY) 
    {
        if (cfg->flags & EDT_OCX_FRAMED)
            rx_filter |= OVERHEAD_ONLY; 
        else
            edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
    }
    edt_reg_write(edt_p, OC192_RCV_FILTER, rx_filter); 

    edt_reg_write(edt_p, OC192_ENABLE, 0);
    edt_reg_write(edt_p, OC192_ENABLE, 0x2);
    edt_reg_write(edt_p, OC192_ENABLE, 0x6);
    edt_reg_write(edt_p, OC192_ENABLE, 0xe);
    edt_reg_write(edt_p, OC192_ENABLE, 0x1e);
    edt_msleep(100);

    /* Received DCM not locked */
    if ((rc = edt_wait_register_bits_high(edt_p, OC192_ENABLE, 0xb0, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"Receive DCM won't lock\n");
        return -1;

    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"Receive DCM Locked\n");



    return 0;

}

int
edt_oc192_laser_on(EdtDev *edt_p, EdtOCConfig *cfg)

{

    EdtXfpSfpRealValue realval;

    if (!cfg->xfp_p)
        cfg->xfp_p = edt_open_xfp_sfp_device(edt_p);

    if (!cfg->xfp_p)
        return 1;

    edt_xfp_sfp_read_current_values(edt_p, cfg->xfp_p);

    edt_xfp_sfp_real_value(edt_p, cfg->xfp_p, EDT_TX_POWER_MW, &realval);

    return (realval.value > 0);    
}

int
edt_oc192_enable_laser(EdtDev *edt_p, EdtOCConfig *cfg)

{

    double t1;
    int first = 1;

    edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 5);

    t1 = edt_timestamp();

    while (!edt_oc192_laser_on(edt_p, cfg))
    {

        if (first)
        {
            edt_msg(EDTLIB_MSG_WARNING,"Waiting for Laser Warmup... This can take up to 30 seconds\n");
            first = 0;
        }

        edt_msleep(500);

    }

    if (!first)
    {
        edt_msg(EDTLIB_MSG_WARNING, "Enabled after %f seconds\n", edt_timestamp() - t1);
    }

    return 0;
}


int
edt_oc192_channel_setup(EdtDev *edt_p, 
                        EdtOCConfig *cfg)

{
    int rc;

    edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);

    /* turn off output as prbs (must be turned off for tagging) */

    edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0);
    /* power up transceiver */

    edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 0x4);

    if (!(cfg->flags & EDT_OCX_PRBS_EN) && (edt_p->channel_no == 1))
    {
        if (rc = edt_wait_register_bits_low(edt_p, OC192_XCVR_CTL_STAT, 0x50, cfg->timeout))
        {
            edt_msg(EDTLIB_MSG_FATAL,"module absent/loss of signal/(module not ready)\n");
            return -1;
        }
    }

    if(cfg->flags & EDT_OCX_LOOPBACK) {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_LOOPBACK);
        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0x9);
    } else if (cfg->flags & EDT_OCX_REMOTE_LPBK)
    {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_REMOTE_LPBK);
        edt_oc192_enable_laser(edt_p, cfg);
    }
    else
    {

        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_NORMAL);
    }

    /* set framer */

    if (edt_p->channel_no == 1)
    {
        edt_oc192_set_framer(edt_p, cfg->flags);

        if (cfg->flags & EDT_OCX_TAGGED_DATA)
            edt_oc192_set_tagging(edt_p,1,cfg->tagid);
    }
    else
    {
        /* turn on memory */
        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0x20);
        /* power up transceiver */

        edt_oc192_enable_laser(edt_p, cfg);

    }

    return 0;
}

int
edt_net10g_channel_setup(EdtDev *edt_p, 
                         EdtOCConfig *cfg)

{
    int rc;

    edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);

    /* turn off output as prbs (must be turned off for tagging) */

    edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0);
    /* power up transceiver */

    edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 0x4);

    if (rc = edt_wait_register_bits_low(edt_p, OC192_XCVR_CTL_STAT, 0x50, cfg->timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"module absent/loss of signal/(module not ready)\n");
        return -1;
    }

    if(cfg->flags & EDT_OCX_LOOPBACK) {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_LOOPBACK);
        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0x19);
    } else {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_NORMAL);
    }

    /* set framer */

    edt_oc192_set_framer(edt_p, cfg->flags);

    if (cfg->flags & EDT_OCX_TAGGED_DATA)
        edt_oc192_set_tagging(edt_p,1,cfg->tagid);

    return 0;
}

int
edt_oc192_wait_for_frame(EdtDev *edt_p, int timeout)

{
    int rc = 0;

    FENTER("edt_oc192_wait_for_frame");

    edt_msg(EDTLIB_MSG_INFO_1,"Waiting for frame CH%d", edt_p->channel_no);

    if (rc = edt_wait_register_bits_high(edt_p, OC192_FRAMING, 
        OC192_FRAME_LOCK , timeout))
    { 
        edt_msg(EDTLIB_MSG_FATAL," - Framing timed out\n");
        rc = -1;
    }
    else
        edt_msg(EDTLIB_MSG_INFO_1," framed\n");

    FRETURN_I("edt_oc192_wait_for_frame", rc);

    return rc;

}

int
edt_oc192_set_tagging(EdtDev *edt_p, int state, int tagid)

{
    u_char mask = 0;

    if (state)
    {
        /* All boards are set up to acquire only selected 
        tag id data, and to transmit on to the 
        next board */

        mask = OC192_TAGS_ONLY | OC192_TAGS_XMIT |
            (tagid & OC192_TAG_MASK);

        /* Only tag 0 board actually generates tags */

        if (tagid == 0)
        {
            mask |= OC192_TAG_ON;

        }

        /* turn off output as prbs (must be turned off for tagging) */

        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0);
        /* power up transceiver */

        edt_reg_write(edt_p, OC192_TAG_CTRL, mask);

        edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 0x5);
        /* turn on laser */


    }
    else
        edt_reg_write(edt_p, OC192_TAG_CTRL, 0);

    return 0;

}

int
edt_oc192_get_overrun(EdtDev *edt_p)

{
    if (edt_p && edt_p->channel_no == 1)
    {
        u_int i = edt_intfc_read(edt_p, 0x94) & 2;
        return (i != 0);
    }
    else
        return FALSE;
}

int
edt_oc192_get_underrun(EdtDev *edt_p)

{
    if (edt_p && edt_p->channel_no & 1)
    {
        u_int i = edt_intfc_read(edt_p, 0x94) & 8;
        return (i != 0);
    }
    else
        return FALSE;
}

/******************************************************
*
* edt_ocx_functions - apply to euther OCM or OC 192 mezzanine boards
*
******************************************************/


/***************************************
*
***************************************/

char *
edt_ocx_default_bitfile(int mezz_id)

{
    char *workfile = NULL;

    switch (mezz_id)
    {
    case MEZZ_OCM:
        workfile = "ocm";
        break;
    case MEZZ_OC192:
        workfile = "oc192";
        break;
    case MEZZ_MSDV:
        workfile = "msdv";
        break;
    case MEZZ_NET10G:
        workfile = "net10g";
        break;

    }

    return workfile;

}

int
edt_ocx_check_interface(EdtDev *edt_p, char *target_file, int force_load)

{
    int rc = 0;
    char *workfile = target_file;
    char *end;

    FENTER_S("edt_ocx_check_interface",target_file);

    edt_get_bitname(edt_p, edt_p->bfd.bitfile_name, sizeof(edt_p->bfd.bitfile_name));

    if (end = strstr(edt_p->bfd.bitfile_name, ".bit"))
            *end = 0;

    if (workfile == NULL || (workfile && (strlen(workfile) == 0)))
    {
        workfile = edt_ocx_default_bitfile(edt_p->mezz.id);

        if (workfile == NULL)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to select interface bitfile for mezzanine %x\n",
                edt_p->mezz.id);
            return -1;
        }
    }

    if (strcmp(edt_p->bfd.bitfile_name, workfile))
    {

        if (force_load)
        {
            edt_msg(EDTLIB_MSG_WARNING, "Loading interface file %s\n",
                workfile);

            rc = (edt_bitload(edt_p, NULL, workfile, 0,0) != 0);        

            /* have to get the board description again */
            if (rc == 0)
                edt_get_board_description(edt_p, FALSE);

        }
        if (rc != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to load bitfile %s\n", workfile);
        }
    }

    /* ok */
    FRETURN_I("edt_ocx_check_interface",rc);

    return rc;

}




int
edt_ocx_lock_clocks(EdtDev *edt_p, int timeout)

{
    switch(edt_p->mezz.id)
    {
    case MEZZ_OCM:
        return edt_ocm_lock_clocks(edt_p, timeout);
    case MEZZ_NET10G:
    case MEZZ_OC192:
        return edt_oc192_lock_clocks(edt_p, timeout);
    case MEZZ_MSDV:
        return edt_msdv_lock_clocks(edt_p, timeout);
    default:
        edt_msg(EDTLIB_MSG_FATAL, "Mezz ID must be OCM or OC192 in edt_ocx_lock_clocks\n");
        return -1;
    }

}



int
edt_ocx_load_default_mezzanine(EdtDev *edt_p, EdtOCConfig *cfg)

{
    switch(edt_p->mezz.id)
    {
    case MEZZ_OCM:
        return edt_ocm_load_default_mezzanine(edt_p, cfg);
    case MEZZ_OC192:
        return edt_oc192_load_default_mezzanine(edt_p, cfg);
    case MEZZ_MSDV:
        return edt_msdv_load_default_mezzanine(edt_p, cfg);
    case MEZZ_NET10G:
        return edt_net10g_load_default_mezzanine(edt_p, cfg);
    default:
        edt_msg(EDTLIB_MSG_FATAL, "Mezz ID must be OCM, OC192, MSDV, or NET10G in edt_ocx_load_fault_mezzanine\n");
        return -1;
    }
}


int
edt_ocx_base_init(EdtDev *edt_p, 
                  EdtOCConfig *cfg)

{
    int rc = 0;
    int force_load = !(cfg->flags & EDT_OCX_SKIP_LOAD);


    FENTER("edt_ocx_init");


    /* identify mezz board */
    if ((rc = edt_get_board_description(edt_p, force_load)) != 0)
    {
        edt_msg(EDTLIB_MSG_FATAL, "Unable to get board description\n");
        return rc;
    }

    if (edt_p->mezz.id != MEZZ_OCM && edt_p->mezz.id != MEZZ_OC192 && edt_p->mezz.id != MEZZ_MSDV &&
        edt_p->mezz.id != MEZZ_NET10G)
    {

        edt_msg(EDTLIB_MSG_FATAL, "Mezzanine ID = %d, OCM or OC192 or MSDV expected\n",
            edt_p->mezz.id);

        edt_print_board_description(edt_p); 

        return -1;
    }


    /* load base bitfile if necessary */
    /* check bitfile */

    if ((rc = edt_ocx_check_interface(edt_p, cfg->intfc, !(cfg->flags & EDT_OCX_SKIP_LOAD))) != 0)
    {
        FRETURN_I("edt_ocx_check_bitfiles",rc);
        return rc;
    }

    /* load default mezzanine if necessary */
    if (edt_p->bfd.mezz_name0[0] == 0)
    {
        edt_ocx_load_default_mezzanine(edt_p, cfg);

    }

    /* Reset channel enables and 100 MHz ref. clock */
    edt_msg(EDTLIB_MSG_INFO_1,"Full init\n");

    edt_set_autodir(edt_p, 0);

    edt_reg_write(edt_p, PCD_CMD, 0); /* reset user xilinx */
    edt_reg_write(edt_p, PCD_CMD, 0); /* reset user xilinx */
    edt_reg_write(edt_p, PCD_CMD, 8);
    edt_reg_write(edt_p, SSD16_CHENL, 0); /* disable all channels */
    edt_reg_write(edt_p, SSD16_LSBL, 0); /* reset lsb first which means msb is first in time */

    /* reset sysclk on both mezzanine xilinx */
    /* note some redundancy for OC192, since only one channel is active at a time */

    edt_reg_write(edt_p, OCM_CH0_ENABLE , 0x0); /* reset all the OCM enables */
    edt_reg_write(edt_p, OCM_CH0_ENABLE , RAM_EN | SYS_EN); /* reset all the OCM enables */
    edt_reg_write(edt_p, OCM_CH0_ENABLE + OFFSET_CH1_BASE, 0x0); /* reset all the OCM enables */
    edt_reg_write(edt_p, OCM_CH0_ENABLE + OFFSET_CH1_BASE, RAM_EN | SYS_EN); /* reset all the OCM enables  RAM_EN not currently used*/
    edt_flush_fifo(edt_p) ;         /* Flush the input fifo */

    if (cfg->flags & EDT_OCX_SWAP)
        edt_reg_write(edt_p, PCD_CONFIG, PCD_BYTESWAP | PCD_SHORTSWAP); 
    else
        edt_reg_write(edt_p, PCD_CONFIG, 0); 

    /* synch clocks */

    /* get plls working */
    rc = edt_ocx_lock_clocks(edt_p, cfg->timeout);

    if (ID_IS_LX(edt_p->devid) && edt_p->mezz.id == MEZZ_OC192 || 
        edt_p->mezz.id == MEZZ_NET10G || edt_p->mezz.id == MEZZ_THREEP)
    {
        if (cfg->line_rate > 48)
                edt_reg_write(edt_p, EDT_PCIE_CFG, 0x54);
        else
                edt_reg_write(edt_p, EDT_PCIE_CFG, 0);
        
    }
    else if (ID_IS_LX(edt_p->devid) && edt_p->mezz.id == MEZZ_OCM)
    {
        edt_reg_write(edt_p, EDT_PCIE_CFG, 0x0);
    }

    FRETURN("edt_ocx_base_init");

    return rc;

}



int
edt_ocx_speed_capable(EdtDev *edt_p, EdtLineRate line_rate)

{
    int rc;

    FENTER("edt_ocx_speed_capable");

    if (edt_p->mezz.id == MEZZ_OC192 || edt_p->mezz.id == MEZZ_NET10G)

        rc = edt_oc192_speed_capable(edt_p->channel_no, line_rate);

    else if (edt_p->mezz.id == MEZZ_OCM)

        rc = edt_ocm_speed_capable(edt_p->channel_no, line_rate);

    else 
        rc = -1;

    FRETURN_I("edt_ocx_speed_capable",rc);

    return rc;

}



int
edt_ocx_has_mezz_bitfile(EdtDev *edt_p, const char *bitfile_name)

{
    int rc = -1;

    FENTER_S("edt_ocx_has_correct_bitfile",bitfile_name);

    if (edt_p->mezz.id == MEZZ_OC192)
    {
        rc = edt_oc192_has_mezz_bitfile(edt_p, bitfile_name);
    }
    else if (edt_p->mezz.id == MEZZ_OCM)
    {
        rc = edt_ocm_has_mezz_bitfile(edt_p, bitfile_name);
    }
    else if (edt_p->mezz.id == MEZZ_NET10G)
    {
        rc = edt_net10g_has_mezz_bitfile(edt_p, bitfile_name);
    }
    else
        rc = -1;


    FRETURN_I("edt_ocx_has_correct_bitfile",rc);

    return rc;

}


const char *
edt_ocx_mezz_filename(EdtDev *edt_p, EdtOCConfig *cfg)

{
    switch(edt_p->mezz.id)
    {
    case MEZZ_OCM:
        return edt_ocm_mezz_filename(edt_p, cfg);
    case MEZZ_OC192:
        return edt_oc192_mezz_filename(edt_p, cfg);
    case MEZZ_NET10G:
        return edt_net10g_mezz_filename(edt_p, cfg);
    }

    return NULL;

}

int
edt_ocx_check_mezz_bitfile(EdtDev *edt_p,
                           EdtOCConfig *cfg)

{  
    int channel = edt_p->channel_no & 1;
    const char *target_bitfile = NULL;
    int rc = 0;
    int force_load = (cfg->flags & EDT_OCX_SKIP_LOAD) == 0;

    FENTER("edt_ocx_check_mezz_bitfile");

    if (edt_p->mezz.id == MEZZ_OC192 && cfg->mezz_0[0])
        target_bitfile = cfg->mezz_0;
    else if (channel == 0 && cfg->mezz_0[0])
        target_bitfile = cfg->mezz_0;
    else if (cfg->mezz_1[0])
        target_bitfile = cfg->mezz_1;


    if (target_bitfile == NULL)
        target_bitfile = edt_ocx_mezz_filename(edt_p,  cfg);

    if (target_bitfile == NULL)
    {
        edt_msg(EDTLIB_MSG_FATAL,"Invalid bit rate %d\n", cfg->line_rate);
        return -1;
    }

    if (edt_ocx_has_mezz_bitfile(edt_p, target_bitfile))
    {
        if (!force_load)
        {
            edt_msg(EDTLIB_MSG_FATAL,
                "Wrong mezzanine bitfile %s for bit rate %d. \nUnset flag EDT_OCX_SKIP_LOAD to load\n",
                target_bitfile, cfg->line_rate);
            return -1;
        }

        edt_msg(EDTLIB_MSG_WARNING,"wrong mezzanine bitfile for line_rate - reloading with %s \n",
            target_bitfile);

        if (edt_p->mezz.id == MEZZ_OCM)
        {
            int flags = BITLOAD_FLAGS_OVR | BITLOAD_FLAGS_OCM;
            if (channel == 1)
                flags |= BITLOAD_FLAGS_CH1;

            rc = edt_bitload(edt_p, NULL, target_bitfile, flags, 0);
        }
        else
        {
            edt_msg(EDTLIB_MSG_INFO_1,"Going to edt_bitload with %s\n", target_bitfile);
            rc = edt_bitload(edt_p, NULL, target_bitfile, BITLOAD_FLAGS_MEZZANINE, 0);
            if (edt_p->mezz.id == MEZZ_OC192)
                if (cfg->dualmode)
                    edt_reg_or(edt_p, OC192_DUAL_CHANNEL_MODE, 4);

        }

    }

    FRETURN_I("edt_ocx_check_mezz_bitfile", rc);

    return rc;
}



int
edt_ocx_set_clock_select(EdtDev *edt_p, EdtLineRate line_rate)

{
    switch(edt_p->mezz.id)
    {
    case MEZZ_OCM:
        return edt_ocm_set_clock_select(edt_p, line_rate);
    case MEZZ_OC192:
        return edt_oc192_set_clock_select(edt_p, line_rate);

    }

    return -1;
}

void
edt_ocx_set_channel_enable(EdtDev *edt_p, int channel, int state)

{
    int channel_mask = (1 << channel);
    edt_reg_set_bitmask(edt_p, SSD16_CHEN, channel_mask, state);

}

void
edt_ocx_set_channel_direction(EdtDev *edt_p, int channel, int do_write)

{
    int channel_mask = (((do_write)?1:0) << channel);
    edt_reg_set_bitmask(edt_p, SSD16_CHDIR, channel_mask, do_write);

}



void
edt_ocx_set_lsbfirst(EdtDev *edt_p, int channel, int state)

{
    int channel_mask = (1 << channel);
    if (state)
        edt_reg_or(edt_p, SSD16_LSB, channel_mask);
    else
        edt_reg_and(edt_p, SSD16_LSB, ~channel_mask);

}

int
edt_ocx_channel_signal_detect(EdtDev *edt_p, int timeout)

{
    u_int reg = OCM_CH0_STATUS;
    u_int bit = SIG_DET;

    switch (edt_p->mezz.id)
    {
    case MEZZ_OC192:
        if (edt_p->channel_no == 1)
        {
            reg = OC192_XCVR_CTL_STAT;
            bit = LOS;
        }
        else
        {
            reg = OCM_CH0_STATUS;
            bit = SIG_DET;
        }
        break;
    case  MEZZ_OCM:
        if (edt_p->channel_no == 1)
        {
            reg += OFFSET_CH1_BASE;
        }
        break;
    }

    return ! edt_wait_register_bits_high(edt_p, reg, bit, timeout);
}


void
edt_ocx_reset_sys_en(EdtDev *edt_p, int channel)

{
    int oc_channel = channel & 1;
    int chen = OCM_CH0_ENABLE + (oc_channel)?OFFSET_CH1_BASE:0;

    edt_reg_write(edt_p, chen, 0x0); /* reset the OCM enables */
    edt_reg_write(edt_p, chen, SYS_EN); /* reset the OCM enables */

}

int
edt_ocx_channel_set_rate(EdtDev *edt_p, EdtOCConfig *cfg)


{
    int channel = edt_p->channel_no & 1;
    int rc = 0;

    FENTER("edt_ocx_channel_set_rate");

    /* make sure board is identified */
    if (edt_p->mezz.id == 0xff)
    {
        if (edt_get_board_description(edt_p, FALSE) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to get board description in edt_ocx_channel_set_rate\n");
            return -1;
        }

    }

    /* check rate */
    if (edt_ocx_speed_capable(edt_p, cfg->line_rate))
    {
        edt_msg(EDTLIB_MSG_FATAL,"This channel %d not capable of this rate %d\n",
            channel, cfg->line_rate);
        return -1;
    }

    /* check bitfile */

    if ((rc = edt_ocx_check_mezz_bitfile(edt_p, cfg)) != 0)
    {
        edt_msg(EDTLIB_MSG_FATAL,"Can't load desired bitfile\n");
        return -1;

    }

    /* load new mezz bitfile if necessary */

    edt_msg(EDTLIB_MSG_INFO_1,"Setting channel %d to rate %d\n", edt_p->channel_no, cfg->line_rate);

    /* disable selected channel */
    edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, 0);

    /* reset lsb first which means msb is first in time */

    edt_ocx_set_lsbfirst(edt_p, edt_p->channel_no, cfg->flags & EDT_OCX_LSB_FIRST);

    edt_flush_channel(edt_p, edt_p->channel_no);

    edt_ocx_reset_sys_en(edt_p, edt_p->channel_no);

    /* If new bitfile, resynch SYS_LOCK for this channel */
    edt_ocx_lock_channel_clock(edt_p, channel, cfg->timeout);

    /* select the correct clock source */

    edt_ocx_set_clock_select(edt_p, cfg->line_rate);

    edt_ocx_enable_framing_errors(edt_p, FALSE);
    edt_ocx_enable_framing_errors(edt_p, TRUE);

    FRETURN("edt_ocx_channel_set_rate");

    return rc;
}

int
edt_ocx_channel_lock_frontend(EdtDev *edt_p,
                              EdtOCConfig *cfg)


{
    if (edt_p->mezz.id == 0xff)
    {
        if (edt_get_board_description(edt_p, FALSE) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to get board description in edt_ocx_channel_lock_frontend\n");
            return -1;
        }

    }

    if (edt_p->channel_no & 1)
    {
        if (edt_p->mezz.id == MEZZ_NET10G)
            return edt_net10g_channel_lock_frontend(edt_p, cfg);
        else if (edt_p->mezz.id == MEZZ_OC192)
            return edt_oc192_channel_lock_frontend(edt_p, cfg);
    }

    return edt_ocm_channel_lock_frontend(edt_p, cfg);

}


int
edt_ocx_channel_setup(EdtDev *edt_p,
                      EdtOCConfig *cfg)


{
    /* make sure board is identified */
    if (edt_p->mezz.id == 0xff)
    {
        if (edt_get_board_description(edt_p, FALSE) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to get board description in edt_ocx_channel_setup\n");
            return -1;
        }

    }
    if (edt_p->channel_no & 1)
        if (edt_p->mezz.id == MEZZ_OC192 || edt_p->mezz.id == MEZZ_NET10G)
            return edt_oc192_channel_setup(edt_p, cfg);

    return edt_ocm_channel_setup(edt_p, cfg);

}

int
edt_ocx_configure(EdtDev *edt_p, 
                  EdtOCConfig *cfg)

{       
    int rc = 0;
    /*
    * configure the OCM board - assume ocmload has been run
    */
    /* check correct version of bitfiles loaded */

    FENTER("edt_ocx_configure");

    edt_msg(EDTLIB_MSG_INFO_1,"configure for speed %d on channel %d\n", 
        cfg->line_rate, edt_p->channel_no);

    /* load baseboard if requested */

    if (cfg->flags & EDT_OCX_FULL_INIT)
    {
        if (edt_ocx_base_init(edt_p, cfg) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to execute base init for unit %d at rate %d\n",
                edt_p->unit_no, cfg->line_rate);
            rc = -1;
        }
    }
    else
    {
        edt_get_board_description(edt_p, FALSE);
    }

    if (rc == 0)
    {
        /* set rate */

        if (edt_ocx_channel_set_rate(edt_p, cfg) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to set rate for unit %d channel %d at rate %d\n",
                edt_p->unit_no, edt_p->channel_no, cfg->line_rate);
            rc = -1;
        }
        /* OK, configure channel parameters */
        else if (edt_ocx_channel_setup(edt_p, cfg) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to set channel parameters unit %d channel %d at rate %d\n",
                edt_p->unit_no, edt_p->channel_no, cfg->line_rate);
            rc = -1;

        }
        else if (edt_ocx_channel_lock_frontend(edt_p, cfg) != 0)
        {
            edt_msg(EDTLIB_MSG_FATAL, "Unable to lock front end unit %d channel %d at rate %d\n",
                edt_p->unit_no, edt_p->channel_no, cfg->line_rate);
            rc = -1;

        }
    }

    FENTER_I("edt_ocx_configure", rc);

    return rc;

}


int
edt_ocx_wait_for_frame(EdtDev *edt_p, int timeout)

{

    if (edt_p->mezz.id == MEZZ_OC192 &&
        edt_p->channel_no & 1)
    {
        return edt_oc192_wait_for_frame(edt_p, timeout);
    } 
    else
    {
        return edt_ocm_wait_for_frame(edt_p, timeout);
    }
}

int
edt_ocx_prepare_for_dma(EdtDev *edt_p, EdtOCConfig *cfg)

{

    //edt_reg_write(edt_p, PCD_CMD, 0);
    printf("PCD_CMD = %x\n", edt_reg_read(edt_p, PCD_CMD));

    edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, FALSE);


    //   if (cfg->writing)
    //   {
    //       edt_reg_write(edt_p, PCD_CMD, 8);
    //       edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, TRUE);
    //   }

    return 0;
}

int
edt_ocx_post_start(EdtDev *edt_p, EdtOCConfig *cfg)

{

    int rc = 0;

    edt_reg_write(edt_p, PCD_CMD, 8);
    edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, TRUE);

    /* wait for framed if collecting framed data */
    if ((cfg->flags & EDT_OCX_FRAMED) && edt_p->channel_no < 2)
    {
        rc = edt_ocx_wait_for_frame(edt_p, cfg->frame_timeout);
    }

    return rc;
}

int
edt_ocx_channel_start_cfg(EdtDev *edt_p, EdtOCConfig *cfg, int n)

{
    int rc = 0;

    FENTER("edt_ocx_channel_start_cfg");

    edt_ocx_prepare_for_dma(edt_p, cfg);

    edt_start_buffers(edt_p, n);

    rc = edt_ocx_post_start(edt_p, cfg);


    FRETURN("edt_ocx_channel_start_cfg");

    return 0;
}

int
edt_ocx_adjust_phase(EdtDev *edt_p, int value)

{
    int rc = 0;

    return rc;
}


int
edt_ocx_channel_start(EdtDev *edt_p)

{

    FENTER("edt_ocx_start");

    edt_msg(EDTLIB_MSG_INFO_1,"Start buffers\n");

    edt_start_buffers(edt_p, edt_p->ring_buffer_numbufs-1) ; /* start the transfers with all the allocated buffers */

    /* enable selected channel */
    edt_reg_write(edt_p, PCD_CMD, 8);

    edt_ocx_set_channel_enable(edt_p, edt_p->channel_no, TRUE);

    edt_msg(EDTLIB_MSG_INFO_1,"enabled\n");


    FRETURN("edt_ocx_start");

    return 0;
}

/* Convenience routines because 16 bit accesses seem
to fail sometimes */

static void
edt_oc192_demux_set_mask_reg(EdtDev *edt_p, u_int reg, u_int column)

{
    edt_reg_write(edt_p,OC192_DEMUX_BITMASK_LO, reg & 0xff);
    edt_reg_write(edt_p,OC192_DEMUX_BITMASK_HI, (reg >> 8) & 0xff);
    edt_reg_write(edt_p,OC192_DEMUX_MASK_ADDR, (0x80 + ( column >> 4 )));

}

static u_int
edt_oc192_demux_get_mask_reg(EdtDev *edt_p, u_int column)

{
    u_int reg;

    edt_reg_write(edt_p, OC192_DEMUX_MASK_ADDR, column >> 4);

    reg = edt_reg_read(edt_p,OC192_DEMUX_BITMASK_RD_LO);
    reg |= edt_reg_read(edt_p,OC192_DEMUX_BITMASK_RD_HI) << 8;

    return reg;

}


int
edt_ocx_demux_nbits(EdtLineRate line_rate)

{
    int n = 0;

    switch(line_rate)
    {

        case STM64_RATE:
        case OC192_RATE:
            n = 192;
            break;

        case OTU2_RATE:
        case OTU2E_RATE:
        case OTU2F_RATE:
            n = 16;
        break;
    
        case STM1_RATE:
        case OC3_RATE:
            n = 3;

            break;
        case STM4_RATE:
        case OC12_RATE:
            n = 12;
            break;
        case STM16_RATE:
        case OC48_RATE:
            n = 48;
            break;
    }
        

    if (n == 0)
        edt_msg(EDTLIB_MSG_FATAL,"Incorrect line rate %d for OC192/OCM\n", line_rate);
    return n;
}

int
edt_oc192_demux_set(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    int n;
    int byte = 0;
    unsigned int reg;

    reg = 0;
    n = edt_ocx_demux_nbits(line_rate);

    if (n == -1)
        return -1;

    for (byte=0;byte < n; byte++)
    {

        reg = (reg << 1);
        reg += (onoff[byte])?0:1;

        if (byte % 16 == 15)
        {
            edt_oc192_demux_set_mask_reg(edt_p, reg, byte);
            reg = 0;
        }
    }

    return 0;
}
int
edt_oc192_demux_get(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    int i = 0;

    int n = edt_ocx_demux_nbits(line_rate);

    if (n == -1)
        return -1;

    for (i=0;i<12;i++)
    {
        int j;

        int reg = edt_oc192_demux_get_mask_reg(edt_p, i << 4);

        for (j=0;j<16;j++)
            onoff[16 * i + j] = 1 ^ (1 & (reg >> (15-j)));

    }


    return 0;

}

int
edt_oc192_demux_chan_enable(EdtDev *edt_p, int channel, int enable)

{
    u_short bits;
    int shift = (0xf - (channel & 0xf));
    u_short mask;

    mask = (u_short) (1 << shift);

    /* get current register value */


    bits = (u_short) edt_oc192_demux_get_mask_reg(edt_p,channel);

    /* bit sense is 0 if on, 1 if off */
    if (enable)
        bits &= ~mask;
    else
        bits |= mask;

    /* write back out */
    edt_oc192_demux_set_mask_reg(edt_p, bits, channel);

    return 0;
}

int
edt_oc192_demux_get_chan_enabled(EdtDev *edt_p, int channel)

{
    u_short bits;

    int shift = (0xf - (channel & 0xf));
    u_short mask;

    mask = (u_short) (1 << shift);

    /* get current register value */
    bits = (u_short) edt_oc192_demux_get_mask_reg(edt_p,channel);

    /* bit sense is 0 if on, 1 if off */

    if (bits & mask)
        return 0;
    else
        return 1;

}

int
edt_ocm_demux_set(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    int n = 48;
    int byte = 0;
    u_short bits[12];
    u_int bitmap_reg = OCM_CH0_DEMUX_BITMAP;

    /* turn on all channels */
    memset(bits,0,sizeof(bits));

    switch (line_rate) {
        case STM1_RATE:
        case OC3_RATE:
            n = 3;

            break;
        case STM4_RATE:
        case OC12_RATE:
            n = 12;
            break;
        case STM16_RATE:
        case OC48_RATE:
            n = 48;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Incorrect line rate %d for OCM demux\n", line_rate);
            return -1;

    }

    if (edt_p->channel_no)
        bitmap_reg = OCM_CH1_DEMUX_BITMAP;

    /* cycle through oring in bits - bit 3 of byte 0 is first channel,
    bit 0 of last byte is last channel */

    /* bit sense is 0 enabled, 1 disabled */

    for (byte=0; byte < n; )
    {
        int val = 0;
        int bit;

        for (bit = 0;bit < 4;bit++)
            val = (val << 1) | ((onoff[byte++]) ? 0 : 1);

        val |= (((byte-1) >> 2) << 4) ;

        edt_reg_write(edt_p, bitmap_reg, val);

    }

    return 0;
}
int
edt_ocm_demux_get(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    int n = 48;
    int i = 0;
    u_short bits[12];
    u_int bitmap_reg = OCM_CH0_DEMUX_BITMAP_READ;

    switch (line_rate) {
        case STM1_RATE:
        case OC3_RATE:
            n = 3;

            break;
        case STM4_RATE:
        case OC12_RATE:
            n = 12;
            break;
        case STM16_RATE:
        case OC48_RATE:
            n = 48;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Incorrect line rate %d for OCM demux\n", line_rate);
            return -1;

    }

    if (edt_p->channel_no)
        bitmap_reg = OCM_CH1_DEMUX_BITMAP_READ;

    for (i=0;i<(n+3)/4;i++)
    {
        edt_reg_write(edt_p, bitmap_reg, i<<4);
        bits[i] = (u_short) edt_reg_read(edt_p, bitmap_reg);
    }

    for (i=0;i < n; i++)
    {
        int whichbyte = i / 4;
        int shift = (3 - (i & 3));

        onoff[i] = (u_char) !(bits[whichbyte] & (1 << shift));

    }

    return 0;

}

int
edt_ocm_demux_chan_enable(EdtDev *edt_p, int channel, int enable)

{
    u_short bits;
    int whichbyte = channel / 4;
    int shift = (3 - (channel & 3));
    u_short mask;
    u_int bitmap_reg = OCM_CH0_DEMUX_BITMAP_READ;

    mask = 1 << shift;
    if (edt_p->channel_no)
        bitmap_reg = OCM_CH1_DEMUX_BITMAP_READ;

    /* get current register value */

    edt_reg_write(edt_p, bitmap_reg, whichbyte << 4);
    bits = edt_reg_read(edt_p, bitmap_reg) & 0xf;

    /* bit sense is 0 if on, 1 if off */
    if (enable)
        bits &= ~mask;
    else
        bits |= mask;

    /* select demux write register */

    bitmap_reg = (edt_p->channel_no)? OCM_CH1_DEMUX_BITMAP: OCM_CH0_DEMUX_BITMAP;

    bits |= (whichbyte << 4);

    /* write back out */
    edt_reg_write(edt_p, bitmap_reg, bits);

    return 0;
}

int
edt_ocm_demux_get_chan_enabled(EdtDev *edt_p, int channel)

{
    u_short bits;
    int whichbyte = channel / 4;
    int shift = (3 - (channel & 3));
    u_short mask;
    u_int bitmap_reg = OCM_CH0_DEMUX_BITMAP_READ;

    mask = 1 << shift;
    if (edt_p->channel_no)
        bitmap_reg = OCM_CH1_DEMUX_BITMAP_READ;

    /* get current register value */

    edt_reg_write(edt_p, bitmap_reg, whichbyte << 4);
    bits = edt_reg_read(edt_p, bitmap_reg) & 0xf;

    if (bits & mask)
        return 0;
    else
        return 1;

}

int
edt_ocx_demux_set(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    if (edt_p->mezz.id == 0xffff)
        edt_get_board_description(edt_p, TRUE);

    if (edt_p->mezz.id == MEZZ_OC192 && edt_p->channel_no == 1)
    {
        return edt_oc192_demux_set(edt_p, line_rate, onoff);
    }
    else
    {
        return edt_ocm_demux_set(edt_p, line_rate, onoff);
    }
}

int
edt_ocx_demux_get(EdtDev *edt_p, EdtLineRate line_rate, u_char *onoff)

{
    if (edt_p->mezz.id == MEZZ_OC192 && edt_p->channel_no == 1)
    {
        return edt_oc192_demux_get(edt_p, line_rate, onoff);
    }
    else
    {
        return edt_ocm_demux_get(edt_p, line_rate, onoff);
    }

}

int
edt_ocx_demux_chan_enable(EdtDev *edt_p, int channel, u_char enable)

{
    if (edt_p->mezz.id == MEZZ_OC192 && edt_p->channel_no == 1)
    {
        return edt_oc192_demux_chan_enable(edt_p, channel, enable);
    }
    else
    {
        return edt_ocm_demux_chan_enable(edt_p, channel, enable);
    }
}

int
edt_ocx_demux_get_chan_enabled(EdtDev *edt_p, int channel)

{
    if (edt_p->mezz.id == MEZZ_OC192 && edt_p->channel_no == 1)
    {
        return edt_oc192_demux_get_chan_enabled(edt_p, channel);
    }
    else
    {
        return edt_ocm_demux_get_chan_enabled(edt_p, channel);
    }
}

/* Enables all channels */

int edt_ocx_demux_reset(EdtDev *edt_p, EdtLineRate line_rate)

{
    u_char onoff[192];

    memset(onoff, 1, sizeof(onoff));

    edt_ocx_demux_set(edt_p, line_rate, onoff);
    
    return 0;
}

/*
* read and print the contents of the auto phase adjust that sets
* up the sample point for the receive clock where the capability exists
*/

int edt_ocx_print_auto_phase(EdtDev *edt_p)
{
    int channel = edt_p->channel_no & 1;
    int base_offset = 0;
    int mezzanine_offset = 0;
    int freq = 0;
    u_char read_byte, ctrl_reg;

    FENTER("edt_ocx_print_auto_phase");
    if (edt_p->mezz.id == MEZZ_OCM)
    {
        if (edt_ocm_has_mezz_bitfile(edt_p, "ethernet.bit") == 0)
        {
            if (channel == 1)
            {
                base_offset = OFFSET_CH1_BASE;
                mezzanine_offset = OFFSET_CH1_MEZ;
            }

            /* write the control register to select normal status */
            ctrl_reg = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset);
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= SIG_STAT;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("RXCLK STAT %02x -", read_byte);
            if (read_byte & NO_RXCLK)
                printf("No receive clock present, ");
            else
                printf("Receive clock present, ");
            if (read_byte & PHASE_OVF)
                printf("DCM phase overflow, ");
            if (read_byte & DCM_LOCK_SET)
                printf("DCM locked, ");
            else
                printf("DCM not locked, ");
            printf("auto state is %d, sample clock is %d\n", (read_byte & DONE_STATE_MSK) >> 2,
                (read_byte & (CLK_F | CLK_R)) );
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= CLK_POS_START;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("First positive edge - %d\n", read_byte);
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= CLK_NEG_EDGE;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("Negative edge - %d\n", read_byte);
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= CLK_NXT_POS;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("Next positive edge - %d\n", read_byte);
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= CLK_FINAL;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("Final auto set position - %d\n", read_byte);
            ctrl_reg &= ~STAT_SEL_MSK;
            ctrl_reg |= SHADOW_CNT;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, ctrl_reg);
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            printf("Current position - %d\n", read_byte);
        }
    }

    FRETURN_I("edt_ocx_print_auto_phase", 0);
    return 0;
}

/*
* read frequency counter - only supported on ocm ethernet at this time
* return channel bitrate in MHz
*/
int edt_ocx_read_frequency(EdtDev *edt_p, EdtOCConfig *cfg)
{
    int channel = edt_p->channel_no & 1;
    int base_offset = 0;
    int mezzanine_offset = 0;
    int freq = 0;
    u_char read_byte;

    FENTER("edt_ocx_read_frequency");
    if (edt_p->mezz.id == MEZZ_OCM)
    {
        if (edt_ocm_has_mezz_bitfile(edt_p, "ethernet.bit") == 0)
        {
            if (channel == 1)
            {
                base_offset = OFFSET_CH1_BASE;
                mezzanine_offset = OFFSET_CH1_MEZ;
            }

            /* write the clear bit to one  after making sure it is zero */
            read_byte = edt_reg_read(edt_p,  OCM_CH0_FREQ_CNT_CTRL + mezzanine_offset);
            read_byte &= ~CLEAR_VALID;
            edt_reg_write(edt_p,  OCM_CH0_FREQ_CNT_CTRL + mezzanine_offset, read_byte);
            read_byte |= CLEAR_VALID;
            edt_reg_write(edt_p,  OCM_CH0_FREQ_CNT_CTRL + mezzanine_offset, read_byte);
            read_byte &= ~CLEAR_VALID;
            edt_reg_write(edt_p,  OCM_CH0_FREQ_CNT_CTRL + mezzanine_offset, read_byte);
            /* wait for valid to set (100us) */
            while ( ((read_byte = edt_reg_read(edt_p, OCM_CH0_FREQ_STATUS + mezzanine_offset)) & FREQ_VALID) == 0) ;
            freq = (int) edt_reg_read( edt_p, OCM_CH0_FREQUENCY + mezzanine_offset);
            /* calculate frequency in MHz
            * Frequency counter counts 0 as the first count
            * the internal FPGA read  clock is divided by 4 in the SLK2511 and then by 2 in the FPGA
            * gate is 100us so Hz is times 10000 but MHz is divide by 100
            */
            freq = ((freq+1) * 8)/ 100; 

            return freq;
        }
    }

    FRETURN_I("edt_ocx_read_frequency",-1);
    return -1;
}


/*
* change the clock phase plus or minus the amount
* passed in change
*/
int edt_ocx_rx_clk_phase(EdtDev *edt_p, int change)
{
    int channel = edt_p->channel_no & 1;
    int base_offset = 0;
    int mezzanine_offset = 0;
    int current_count = 0;
    u_char read_byte;

    FENTER("edt_ocx_rx_clk_phase");
    if (edt_p->mezz.id == MEZZ_OCM)
    {
        if (edt_ocm_has_mezz_bitfile(edt_p, "ethernet.bit") == 0)
        {
            if (channel == 1)
            {
                base_offset = OFFSET_CH1_BASE;
                mezzanine_offset = OFFSET_CH1_MEZ;
            }

            /* read the current position from the shadow count */
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset);
            read_byte &= ~(PRG_PS_EN | STAT_SEL_MSK) ; /* reset the ps_en if set */
            read_byte |= SHADOW_CNT;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, read_byte);
            /* read the count */
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            current_count = (int) (read_byte & 0xff); /* make it an int */
            if ( (current_count + change) < 0)
            {
                /*
                printf("Proposed RXCLK phase change %d to %d makes final < 0, setting phase to 0\n",
                change, current_count);
                */
                change = - current_count;
            }
            if ( (current_count + change) > 255)
            {
                /*
                printf("Proposed RXCLK phase change %d to %d makes final > 255, setting phase to  max at 255\n",
                change, current_count);
                */
                change = - current_count;
            }
            /* set to increment if change is positive  and set status read to basic status */
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset);
            read_byte &= ~STAT_SEL_MSK ;
            read_byte |= SIG_STAT ; 
            if (change > 0) 
            {
                read_byte |=  PRG_PS_INC;
            }
            else
            {
                read_byte &=  ~PRG_PS_INC;
                change = -change;
            }
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, read_byte);
            while(change--)
            {
                /* inc/dec by one - strobe ps_en */
                read_byte |= PRG_PS_EN;
                edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, read_byte);
                read_byte &= ~PRG_PS_EN;
                edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, read_byte);
                /* wait until the state machine comes back to the done state */
                while (((edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset)) & DONE_STATE_MSK) != STATE_DONE);
            }
            /* read the current shadow count and return */
            read_byte &= ~STAT_SEL_MSK ;
            read_byte |= SHADOW_CNT;
            edt_reg_write(edt_p,  OCM_CH0_RX_CLK_CTRL + mezzanine_offset, read_byte);
            /* read the count */
            read_byte = edt_reg_read(edt_p,  OCM_CH0_RX_CLK_STAT + mezzanine_offset);
            FRETURN_I("edt_ocx_rx_clk_phase", read_byte);
            return(read_byte);
        }
    }

    FRETURN_I("edt_ocx_rx_clk_phase",-1);
    return -1;
}

int
edt_ocx_clear_demux(EdtOcxDemux *demux)

{
    memset(demux, 0, sizeof(EdtOcxDemux));
    return 0;
}

int
edt_ocx_parse_demux(EdtOcxDemux *demux, const char *word, char *errorstr)

{

    u_char DCBA[4];
    int len = 0;
    int maxlen = 4;
    const char *cp = word;
    int disable = FALSE;
    int i;
    u_char *pvec;
    int off;
    u_char is_stm = TRUE;

    memset(DCBA,0,sizeof(DCBA));

    switch (demux->rate)
    {
    case 1:
    case 3:
        maxlen = 1;          
        break;

    case 4:
    case 12:
        maxlen = 2;
        break;
    case 16:
    case 48:
        maxlen = 3;
        break;
    case 64:
    case 192:
        maxlen = 4;
        break;

    case OTU2_RATE:
    case OTU2E_RATE:
    case OTU2F_RATE:
        maxlen = 1;
        is_stm = FALSE;
        break;

    default:
        sprintf(errorstr, "Rate %d not defined for demux\n",demux->rate);
        return -1;

    }

    /* remove parens and commas */

    if (*cp == '-') 
    {
        disable = TRUE;
        cp++;
    }

    if (*cp == '(')
        cp++;

    while (*cp && *cp != ')' && len < 4)
    {
        if (*cp >= '0' && *cp <= '4')
        {
            DCBA[len] = *cp - '0';
            len++;
        }
        else
        {
            sprintf(errorstr, "Unexpected character %c at %d in %s, should be 0-4\n",
                *cp, cp - word, word);
            return -1;

        }

        cp++;
        if (*cp == ',')
            cp++;
        else if (*cp && *cp != ')')
        {
            sprintf(errorstr, "Unexpected character %c at %d in %s\n",
                *cp, cp - word, word);
            return -1;
        }
    }


    if (len > maxlen)
    {
        sprintf(errorstr, "%s can only have %d value%s in notation\n", edt_ocx_rate_name(demux->rate),maxlen,(maxlen > 1)?"s":"");
        return -1;
    }

    if (is_stm)
    {
        if (DCBA[maxlen-1] == 4)
        {
            sprintf(errorstr, "%s last value should be 1-3 in %s\n", edt_ocx_rate_name(demux->rate), word);
            return -1;
        }
    }

    sprintf(errorstr, "DCBA = (");
    for (i=0;i<maxlen-1;i++)
        sprintf(errorstr + strlen(errorstr), "%d,", DCBA[i]);
    sprintf(errorstr + strlen(errorstr), "%d)\n", DCBA[maxlen-1]);

    if (disable)
        pvec = demux->disable;
    else
        pvec = demux->enable;

    switch (demux->rate)
    {
    case 1:
    case 3:
        break;

    case 4:
    case 12:
        if (DCBA[0] == 0)
        {
            for (i=0;i<12;i++)
                pvec[i] = 1;
        }
        else if (DCBA[1] == 0)
        {
            /* STM-1 (vC-4) */
            off = (DCBA[0]-1);
            pvec[off] = 1;
            pvec[off+4] = 1;
            pvec[off+8] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-1 # %d\n", off+1);
        }
        else
        {
            off = (DCBA[0]-1) + 4 * (DCBA[1]-1);
            pvec[off] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-0 # %d\n", off+1);
        }
        break;

    case 16:
    case 48:
        if (DCBA[0] == 0)
        {
            for (i=0;i<48;i++)
                pvec[i] = 1;
        }
        else if (DCBA[1] == 0)
        {
            /* STM-4 (vC-4-4c) */
            off = 4 * (DCBA[0]-1);
            for (i=0;i<4;i++)
            {
                pvec[off+i] = 1;
                pvec[off+16+i] = 1;
                pvec[off+32+i] = 1;
            }
            sprintf(errorstr + strlen(errorstr), "STM-4 # %d\n", off/4 + 1);
        }
        else if (DCBA[2] == 0)
        {
            /* STM-1 (vC-4) */
            off = 4 * (DCBA[0]-1) + (DCBA[1]-1);
            pvec[off] = 1;
            pvec[off+16] = 1;
            pvec[off+32] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-1 # %d\n", off+1);
        }
        else
        {
            off = 4 * (DCBA[0]-1) + (DCBA[1]-1) + 16 * (DCBA[2]-1);
            pvec[off] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-0 # %d\n", off+1);
        }
        break;

    case 64:
    case 192:
        if (DCBA[0] == 0)
        {
            for (i=0;i<192;i++)
                pvec[i] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-64 \n");
        }
        else if (DCBA[1] == 0)
        {
            /* STM-16 (vC-4-16c) */
            off = 16 * (DCBA[0]-1);
            for (i=0;i<16;i++)
            {
                pvec[off+i] = 1;
                pvec[off+64+i] = 1;
                pvec[off+128+i] = 1;
            }     
            sprintf(errorstr + strlen(errorstr), "STM-16 # %d\n", off / 16 + 1);
        }
        else if (DCBA[2] == 0)
        {
            /* STM-4 (vC-4-4c) */
            off = 16 * (DCBA[0]-1) + 4 * (DCBA[1]-1);
            for (i=0;i<4;i++)
            {
                pvec[off+i] = 1;
                pvec[off+64+i] = 1;
                pvec[off+128+i] = 1;
            }
            sprintf(errorstr + strlen(errorstr), "STM-4 # %d\n", off/4 + 1);
        }
        else if (DCBA[3] == 0)
        {
            /* STM-1 (vC-4) */
            off = 16 * (DCBA[0]-1) + 4 * (DCBA[1]-1) + (DCBA[2]-1);
            pvec[off] = 1;
            pvec[off+64] = 1;
            pvec[off+128] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-1 # %d\n", off+1);
        }
        else
        {
            off = 16 * (DCBA[0]-1) + 4 * (DCBA[1]-1) + (DCBA[2]-1) + 64 * (DCBA[3]-1);
            pvec[off] = 1;
            sprintf(errorstr + strlen(errorstr), "STM-0 # %d\n", off+1);
        }
        break;

    case OTU2_RATE:
    case OTU2E_RATE:
    case OTU2F_RATE:
        off = DCBA[0]-1;
        pvec[off] = 1;
        pvec[off+4] = 1;
        pvec[off+8] = 1;
        pvec[off+12] = 1;

        break;

    }

    return 0;
}

char * edt_ocx_print_byte_array(u_char *pvec, EdtLineRate rate, char *buf)

{
    int n = edt_ocx_demux_nbits(rate);

    static char pbuf[256];

    int on = 0;
    int start = 0;
    char *bp;

    int i;

    if (buf == NULL)
        buf = pbuf;

    bp = buf;

    for (i=0;i<n;i++)
    {
        if ((pvec[i] &&  !on) ||
            (!pvec[i] && on))
        {
            if (on)
            {
                if (start == i-1)
                    sprintf(bp, "%d ", i-1);
                else
                    sprintf(bp, "%d-%d ", start, i-1);
                bp += strlen(bp);
            }
            else
            {
                start = i;
            }

            on = !on;
        }
        else if ((i == n-1) && on)
        {
            sprintf(bp, "%d-%d ", start, i);
            bp += strlen(bp);

        }
    }

    return buf;

}



int edt_ocx_demux_print(EdtOcxDemux *demux)

{
    char buf[256];


    printf("Current  : %s\n",edt_ocx_print_byte_array(demux->current_values, demux->rate, buf));
    printf("Enable   : %s\n",edt_ocx_print_byte_array(demux->enable, demux->rate, buf));
    printf("Disable  : %s\n",edt_ocx_print_byte_array(demux->disable,demux->rate, buf));

    return 0;

}



double edt_ocx_get_data_rate(EdtLineRate rate)

{
    double r = 1000000.0;
    switch (rate)
    {
    case STM0_RATE:
        r *= 4.86;
        break;

    case GIGE_RATE:
        r *= 125.0;
        break;

    case OC3_RATE:
    case STM1_RATE:
        r *= 19.44;
        break;

    case OC12_RATE:
    case STM4_RATE:
        r *= 77.76;
        break;

    case OC48_RATE:
    case STM16_RATE:
        r *= 311.04;
        break;

    case OTU1_RATE:
        r *= 333.26;
        break;

    case OC192_RATE:
    case STM64_RATE: 
        r *= 1244.16;
        break;

    case GIG10E_RATE:
        r *= 1289.06;
        break;

    case OTU2_RATE:
        r *= 1338.65;
        break;

    case OTU2E_RATE:
        r *= 1386.96;
        break;

    }

    return r;
}

---