by Jash Tracey | May 17, 2013
Features Sixteen E1 / T1 line interfaces Four E3 / T3 line interfaces Sixteen LVDS (TIA644 standard) or RS422 differential inputs / output (input or output in groups of four) Large Xilinx FPGA (provided by EDT PCIe8 LX, PCI GS, or PCI SS main board – see details...
by Jash Tracey | Apr 17, 2013
Features Sixteen E1 / T1 line interfaces Four E3 / T3 line interfaces Sixteen ECL differential inputs / outputs Large Xilinx FPGA (provided by EDT PCIe8 LX, PCI GS, or PCI SS main board – see details below) Two large synchronous static memory banks or one memory...
