EDT PDV driver version 5.4.1.1 packages released

EDT PDV driver version 5.4.1.1 packages released

2013/04/25: The EDT version 5.4.1.1 driver & SDK packages for EDT digital imaging boards are now available for download.

The new packages include numerous updates to libraries, utilities and examples, as well as recommended firmware updates for most PCI Express series image capture and simulator boards.*

For a complete list of changes, see the changelog. Briefly, the changes include:

  • New pdv_enable_framesynch() API and method_framesynch directive, enable new frame out-of-synch detection method.
  • Improved timeout detection on PCIe framegrabber boards, via firmware logic that suspends ROI line padding unless explicitly enabled (requires a firmware update).
  • Firmware support for PCIe8 DVa C-Link DDR2 on-board memory.
  • New or updated camera support: Dalsa Falcon 2 (special 80-bit modes), Hamamatsu OrcaFlash 4.0 (5×16 mode), AVT Bonito, Basler Racer.
  • New feature in the Windows pdvshow application, to allow viewing of pixel data in both decimal and hexidecimal format.
  • Fixed pdvshow Autonumber (file save) feature.
  • Windows Camera Link serial dll corrections to unit / channel addressing in non-zero (defaul) cases.
  • Camera Link serial deadlock fix.
  • Updated Camera Configuration Guide, including discussion of new directives and methods for framesync and new above cameras’ deinterleave methods.
  • Various fixes and improvements to pdvshow, libraries, the utilities and example applications.

Most of the above is described in the pdv changelog. But the new framesync method bears special mention. This consists of a collection of new API subroutines, and one new camera configuration file directive that provide an alternate method for checking for an image out-of-synch condition.

Presently, the hardware issues a timeout if data underruns occur, and if you check for timeouts and apply recommended recovery methods, all will usually be well. But overruns can also occur, which can problematic as they can cause data to be skewed but won’t result in a timeout. And in hardware continuous mode (enabled if continuous: 1 or fv_once: 1 is present in the config file), hardware timeouts can not be relied on to detect data underruns. Furthermore, in PCIe boards running rev. 13 or earlier firmware, ROI line padding was always on by default, which could also mask timeouts and occasionally lead to a persistent out-of-synch condition.

As of 5.4.1.1, the new config directive method_frameync and library subroutinespdv_enable_framesync(), pdv_check_framesync(), and pdv_framesync_mode() provide a supplemental method for verifying frame synchronization. The method takes advantage of the IRIG2 header functionality that has been available since rev. 10 PCIe firmware. This functionality, when enabled, adds 16 bytes of footer data to every frame, including a magic number and frame counter (as well as an IRIG timestamp, if an IRIG signal is connected.)pdv_enable_framesync() enables this footer, so pdv_check_framesync() can be used to find out if the magic number is present and in the right place.

Does all this mean you have to rewrite your code to use the new functionality? Not necessarily. The new method_framesync config file directive can be used not just to turn on the framesync footer — with the EMULATE_TIMEOUT argument, it will also to cause the library to issue a timeout when the frame footer out of synch condition is detected. If your application is already checking for timeouts after every frame (it should) then the timeout count will be increased if the frame magic number is not where it should be, even if the hardware doesn’t detect an underrun.

But do you really need it? In most cases, probably not. In fact just updating your PCI Express*framegrabber with rev. 14 firmware will improve data underrun (timeout) detection, since it switches ROI padding to not be the default. So we recommend doing that in any case, and if you still see undetected underruns (generally manifesting as persistently out of synch frames) OR if you use config files with fv_once: 1 or continuous: 1, then try enabling framesync detection by adding the method_framesync: EMULATE_TIMEOUT or using the subroutines.

Firmware

There are two ways to get the new firmware:

1) Download and install the v.5.4.1.1 or later software package, then run

pciload update

OR if you want to update your board’s firmware without updating your installed PDV software package:

2) Get the firmware for your specific board(s) from the links below. For all of the below EXCEPT the PCIe4 DVa FOX/F4 full mode bitfile, save the downloaded file(s) in the directory:

  • On Windows: c:\EDT\pdv\flash\xc5vlx30t (Windows)
  • On Linux / MacOS: /opt/EDTpdv/flash/xc5vlx30t

For PCIe4 DVa FOX / F4 full mode bitfile, (pe4dvafox_fm-01.bit), save the file in:

  • On Windows: c:\EDT\pdv\flash\xc5vlx50t (Windows)
  • On Linux / MacOS: /opt/EDTpdv/flash/xc5vlx50t

Then navigate to your EDT installation directory (usually c:\EDT\Pdv or /opt/EDTpdv) and from the command line, run the command from the table below

Note: The ‘a‘ in board model names is highlghted red to help avoid confusion between ‘a‘ and non-‘a’ model boards. Flashing your board with the wrong FPGA file can render it non-operational

Board, mode Firmware file To update, run
PCIe8 DVa C-Link, base/med pe8dvacamlk-14.bit pciload pe8dvacamlk-14
PCIe8 DVa C-Link, full pe8dvacamlk_fm-14.bit pciload pe8dvacamlk_fm-14
PCIe8 DVa C-Link, full w/DDR pe8dvacamlkddr_fm-14.bit pciload pe8dvacamlkddr_fm-14
PCIe8 DV C-Link, base pe8dvcamlk2-14.bit pciload pe8dvcamlk2-14
PCIe8 DV C-Link, full pe8dvcamlk2_fm-14.bit pciload pe8dvcamlk2_fm-14
PCIe4 DVa C-Link, base/med pe4dvacamlk-14.bit pciload pe4dvacamlk-14
PCIe4 DVa C-Link, full pe4dvacamlk_fm-14.bit pciload pe4dvacamlk_fm-14
PCIe8 DVa CLS, base/med pe8dvaclsim-03.bit pciload pe8dvaclsim-03
PCIe8 DVa CLS, full pe8dvaclsim_fm-01.bit pciload pe8dvaclsim_fm-01
PCIe4 DVa FOX/F2, base pe4dvafox-03.bit pciload pe4dvafox-03
PCIe4 DVa FOX/F4, base pe4dvafox-01.bit pciload pe4dvafox-01

If you have more than one EDT board in your system, you may need to specify the -u <unit>argument. For details about -u and other arguments, see the Firmware section in the PCI Express Digital Video Framegrabbers users guide.

For technical information, contact technical support.

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* Note: The new firmware is not available for the legacy PCIe4 DV C-Link (no ‘a’) or rev 10 or lower PCIe8 DV C-Link.