PCIe8 G3 S5-40G

PCIe8 G3 S5-40G
Altera Stratix V FPGA | 40Gbps QSFP+

The PCIe8 G3 S5-40G is a fast, versatile PCI Express (PCIe, Gen3) x8 interface with one 40G QSFP+ and up to two 10G SFP/+ ports. It supports 1/10/40GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f.

Each port of the PCIe8 G3 S5-40G links to the FPGA for serialization / deserialization (SERDES) and clock recovery. Each port has its own reference clock, programmable for 10–210 MHz.

The single FPGA is an Altera Stratix V GX (A3, A5, A7, or A9) with access to two independent 4 GB blocks of DRAM (DDR3), which can act as data buffers. The FPGA provides up to 16 independent DMA channels via EDT FPGA configuration files.

A time code input (1 pps or IRIG‑B) also is included, with an option for either DB9 or BNC cabling.

EDT FPGA configuration files are included to support 1GbE and 10GbE at the PHY layer; OC3/12/48/192 and OTU1/2/2e/2f (raw, framed, framed and descrambled); and demultiplexing. Custom files can be requested.

Related Products

EDT PCIe8 G3 S5 10G Communication / FPGA board

PCIe8 G3 S5-10G

The PCIe8 G3 S5-10G is a fast, versatile PCI Express (PCIe, Gen3) x8 interface with up to four 10G SFP/+ ports. It supports 1/10GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. The ports of the PCIe8 G3 S5-10G link to the FPGA for… Read more »

EDT PCIe8 G3 A5-10G Communication Interface

PCIe8 G3 A5-10G

The PCIe8 G3 A5-10G is a fast, versatile low-profile PCI Express (PCIe, Gen3) x8 interface, available with either a full or a half-height back panel. It has up to two 10G SFP/+ ports and supports 1/10GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f…. Read more »

Time Distribution Board

Time distribution board

Time Distribution is an auxiliary board that receives a time code signal (from a 1 pps or IRIG-B time code source) and distributes it to multiple EDT main boards to timestamp data. One header allows communication from the main board… Read more »