The SRXL is a mezzanine board that pairs with an EDT main board (for PCI or PCI Express) to accept simultaneous RF inputs in the L-band range of 925 to 2175 MHz and the IF range of 65 to 225 MHz.
Each input is processed with a tunable quadrature down-converter. The resulting baseband I and Q signals are low-pass filtered and digitized with 12-bit precision at programmable sample rates up to 65 MHz.
The resulting four channels of digital sample data are available as inputs to the Xilinx Spartan 3 FPGA, which is programmable to perform signal processing or to serve as a configurable switch matrix to route data to the main board and up to two 4-channel digital down-converter Graychips (GC4016).
The SRXL is similar to the SRXL2. The main differences are shown below.
SRXL SRXL2 FPGA Xilinx Spartan 3 Xilinx Virtex 4 SX Graychips 2 4 or 0 L-band 925 to 2175 MHz (66 MHz bandwidth); 5 MHz tuning resolution 900-2250 MHz (115 MHz bandwidth); 500 kHz tuning resolution IF
65 to 225 MHz (46 MHz bandwidth); 1 MHz tuning resolution 160 or 140 MHz
(70 MHz bandwidth),
70 MHz (40 MHz bandwidth), or other frequencies below 90 MHz with a direct sampling path
Sample clock Programmable to any frequency from 1 to 65 MHz Programmable to any frequency from 10 to 250 MHz Time code input
None 1 pps, IRIG-B, or other other inputs, with user-configurable output Main board
PCIe8 LX, PCI GS, or (legacy) PCI SS PCIe8 LX or PCI GS