Programmable L-band and IF receiver

SRXL2 Mezzanine

The SRXL2 is a mezzanine board that pairs with an EDT main board to receive and process the following inputs:

  • L-band inputs of 900 to 2250 MHz
  • IF inputs of 160, 140, 70, or 21.4 MHz
  • IF inputs below 90 MHz with a direct sampling path
  • Any of the above L-band and IF inputs simultaneously

The user-programmable Xilinx Virtex 4 XC4VSX55 FPGA can perform signal processing or serve as a configurable switch matrix to route data to four digital down-converter Graychips (GC4016).The board also has a TCXO 10-MHz reference clock which can be set for internal or external use.

The SRXL2 can be ordered with either a PCI GS or PCIe8 LX main board for bus connectivity and additional FPGA resources.

The SRXL2 is similar to the SRXL. The main differences are shown below.

FPGA Xilinx Spartan 3 Xilinx Virtex 4 SX
Graychips 2 4 or 0
L-band 925 to 2175 MHz (66 MHz bandwidth); 5 MHz tuning resolution 900-2250 MHz (115 MHz bandwidth); 500 kHz tuning resolution


65 to 225 MHz (46 MHz bandwidth); 1 MHz tuning resolution 160 or 140 MHz
(70 MHz bandwidth),
70 MHz (40 MHz bandwidth), or other frequencies below 90 MHz with a direct sampling path
Sample clock Programmable to any frequency from 1 to 65 MHz Programmable to any frequency from 10 to 250 MHz
Time code input


None 1 pps, IRIG-B, or other other inputs, with user-configurable output
Main board


PCIe8 LX, PCI GS, or (legacy) PCI SS (legacy) PCI GS or PCIe8 LX

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